Browsing by Author "Tsai, Fu-Yi"

Now showing 1 - 4 of 4

Electrooptical Properties of InGaAs/GaAs Strained Single Quantum Wells
(2000)
Lu, Chien-Rong
;
Lou, Shry-Fong
;
Cheng, Hung-Hsiang
;
Lee, Chien-Ping
;
Tsai, Fu-Yi
The electrooptical properties of (100) and (111)B InGaAs/GaAs strained single quantum wells have been studied by the photoreflectance spectroscopy at various temperatures and under different biases. There is a Si delta-doping sheet under the GaAs surface to screen the surface built-in electric field from the quantum well. The spectral features consist of the excitonic interband transitions in the quantum well, and the Franz-Keldysh oscillations from the band edge transitions of the GaAs barrier near the surface. The piezoelectric field tilts the (111)B single quantum well toward the Si delta-doping and causes subband filling by the electrons from the delta-doping centers. With a proper external bias to repel electrons from the tilted quantum well, the excitonic interband transition in the (111)B system is enhanced.
Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process
(2012)
Dai, Chia-Tsen
;
Chiu, Po-Yen
;
Ker, Ming-Dou
;
Tsai, Fu-Yi
;
Peng, Yan-Hua
The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.
On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process
(2009)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
Tsai, Fu-Yi
;
Chang, Yeong-Jar
;
電子工程學系及電子研究所
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 degrees C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
(2009)
Chiu, Po-Yen
;
Ker, Ming-Dou
;
Tsai, Fu-Yi
;
Chang, Yeong-Jar
;
電子工程學系及電子研究所
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.