Browsing by Author "Tsai, Jung-Ruey"

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Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors with and without Film Profile Engineering by TCAD Simulation
(2015)
Tsai, Jung-Ruey
;
Lin, Horng-Chih
;
Chang, Hsiu-Fu
;
Shie, Bo-Shiuan
;
Wen, Ting-Ting
Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (>= 10(19) cm(-3)) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].
Effect of dose loss of phosphorus on capacitance-voltage characteristics of n-type poly-Si junctionless thin-film transistors
(2017-01-01)
Tsai, Jung-Ruey
;
Wen, Ting-Ting
;
Lin, Horng-Chih
;
交大名義發表
;
電子工程學系及電子研究所
This study examines the effects of the dose loss of phosphorus on the capacitance-voltage characteristics of an n-type polycrystalline silicon junctionless (JL) transistor using experimental, analytical and simulated analyses. It clearly demonstrates that the gate voltage increases as the doping concentration in the channel of the JL transistor decreases, maintaining constant capacitance because the depletion region is easily formed at the surface of the channel with a low doping concentration. The critical gate voltage (V-GC) is defined as the applied gate voltage that induces the gate capacitance at the kink of the C-V curve. The simulated results clearly suggest that the critical gate voltage increases linearly with the percentage of dose loss of phosphorus.
ENGINEERED THRESHOLD VOLTAGE IN ALGAN/GAN HEMTS FOR NORMALLY-OFF OPERATION
(2015)
Tsai, Jung-Ruey
;
Chang, Yi-Sheng
;
Wei, Kuo-Shu
;
Wen, Ting-Ting
;
奈米中心
This work proposed the normally-off gate-recessed AlGaN/GaN high electron mobility transistors (HEMTs) with more suitable threshold voltages by adjusting the Al mole fraction in the various AlGaN layer thickness under the gate region. It is found that the slope of threshold voltage versus Al mole fraction curves is decreased with decreasing the thickness of AlGaN layer due to the decrease of piezoelectric effect on 2DEG concentration.
Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels
(2014-04-01)
Tsai, Jung-Ruey
;
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A novel gate-all-around (GAA) poly-Si floating-gate (FG) memory device with triangular nanowire (NW) channels was fabricated and characterized in this work. The enhanced electric field around the corners of the NW channels boosts more electrons tunneling through the tunnel oxide layer during programming and erasing (P/E) processes, and thus the operation voltage markedly decreases. Furthermore, the nonlocalized trapping feature characteristic of the FG makes the injection of electrons easier during the programming operation, which was demonstrated by technology computer-aided design (TCAD) simulations. (C) 2014 The Japan Society of Applied Physics
Impact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistors
(2016-04)
Zhong, Chia-Wen
;
Lin, Horng-Chih
;
Tsai, Jung-Ruey
;
Liu, Kou-Chen
;
Huang, Tiao-Yuan
In this work, we study the impact of gate dielectrics on the characteristics of bottom-gated tin-oxide thin-film transistors annealed in an oxygen ambience at 300 degrees C for various periods. SiO2, HfO2, and Al2O3 are employed as the gate dielectric in the test devices. The results show that the devices will start exhibiting p-type conduction behavior as the annealing reaches a specific time period which is closely related to the underlying gate dielectric, and the device characteristics can be improved as the annealing proceeds further. Nonetheless, a prolonged annealing may cause degradation of the devices. High hole mobility (3.33 cm(2)V(-1)s(-1)), low threshold voltage (1.95 V), and excellent I-on/I-off ratio (similar to 10(4)) are achieved on SnO TFTs with a SiO2 gate dielectric after an annealing of 30 min. (C) 2016 The Japan Society of Applied Physics
Impact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistors
(2016-04-01)
Zhong, Chia-Wen
;
Lin, Horng-Chih
;
Tsai, Jung-Ruey
;
Liu, Kou-Chen
;
Huang, Tiao-Yuan
In this work, we study the impact of gate dielectrics on the characteristics of bottom-gated tin-oxide thin-film transistors annealed in an oxygen ambience at 300 degrees C for various periods. SiO2, HfO2, and Al2O3 are employed as the gate dielectric in the test devices. The results show that the devices will start exhibiting p-type conduction behavior as the annealing reaches a specific time period which is closely related to the underlying gate dielectric, and the device characteristics can be improved as the annealing proceeds further. Nonetheless, a prolonged annealing may cause degradation of the devices. High hole mobility (3.33 cm(2)V(-1)s(-1)), low threshold voltage (1.95 V), and excellent I-on/I-off ratio (similar to 10(4)) are achieved on SnO TFTs with a SiO2 gate dielectric after an annealing of 30 min. (C) 2016 The Japan Society of Applied Physics
Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire
(2013-10-07)
Lee, Ko-Hui
;
Tsai, Jung-Ruey
;
Chang, Ruey-Dar
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
A gate-all-around polycrystalline silicon nanowire (NW) floating-gate (FG) memory device was fabricated and characterized in this work. The cross-section of the NW channels was intentionally made to be triangular in shape in order to study the effects of the corners on the device operation. Our results indicate that the channel corners are effective in lowering the programming and erasing (P/E) operation voltages. As compared with the charge-trapping type devices, a larger memory window is obtained with the FG scheme under low-voltage P/E conditions. A model considering the nature of the charge storage medium is proposed to explain the above findings. (C) 2013 AIP Publishing LLC.
Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stress
(2015)
Tsai, Jung-Ruey
;
Wen, Ting-Ting
;
Yang, Shao-Ming
;
Sheu, Gene
;
Chang, Ruey-Dar
This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 mu A conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.