Browsing by Author "Tsai, Ming-Fu"

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A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
;
Fan, Ming-Long
;
Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
Criteria for Plasmon-Enhanced Electron Drag in Si Metal-Oxide-Semiconductor Devices
(2015-03-01)
Chen, Ming-Jer
;
Hsieh, Shang-Hsun
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Liao, Yu-Chiao
;
Chen, Chuan-Li
;
Tsai, Ming-Fu
Plasmons in the highly doped source and drain regions of silicon field-effect transistors can strongly drag channel electrons via long-range collective Coulomb interactions and cause deteriorations in overall device performances. To examine such interactions, two different methods have been published: 1) sophisticated device simulations and 2) carefully calibrated experiments. To provide a more transparent understanding, we propose a third method in terms of two criteria: 1) one for the occurrence of the plasmon resonance and 2) the other for the strength of the plasmons. The former is determined based on our published dragged mobility data due to the interface plasmons and the bulk plasmons in gate. The latter makes use of our more recently experimentally extracted potential fluctuations due to plasmons in crystalline silicon. The effects of the temperature on the criteria are considered. It is a straightforward task to confirm that for a channel density larger than approximately 5 x 10(12) cm(-2), the source and drain plasmons act as key limiters in silicon device scaling. Therefore, the underlying device physics, modeling, simulations, experimental analyses, and data interpretation may be inaccurate if the limiting factors are not incorporated.
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
(2013)
Tsai, Ming-Fu
;
Fan, Ming-Long
;
Pao, Chia-Hao
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.
Diamagnetic Response of Exciton Complexes in Semiconductor Quantum Dots
(2008-12-31)
Tsai, Ming-Fu
;
Lin, Hsuan
;
Lin, Chia-Hsien
;
Lin, Sheng-Di
;
Wang, Sheng-Yun
We report measurements of diamagnetic shifts for different exciton complexes confined in small InAs quantum dots. The measured diamagnetic responses are sensitive to the number of carriers in the exciton complexes, with systematic differences between neutral excitons, biexcitons, and trions. Theoretical calculations suggest that such systematic differences arise from very different extents of electron and hole wave functions confined in small quantum dots. The measured magnetic response of Coulomb energies is found to vary with the cube of the wave function extent, and can be a sensitive probe to the electron-hole wave function asymmetry.
Two Competing Limiters in MOSFETs Scaling: Neutral Defects and S/D Plasmons
(2016)
Hsieh, Shang-Hsun
;
Hung, Jo-Chun
;
Weng, Heng-Jui
;
Tsai, Ming-Fu
;
Chiang, Chih-Chi
On the industrial HKMG silicon MOSFETs with different channel lengths L down to 14 nm, we present high-resolution TEM cross-section images to highlight interstitial defects in the channel near the source and drain. To examine such neutral defects, we devise a new 2D microscopic scattering model and use it to extract the apparent neutral defects density from the measured inversion-layer effective mobility. We find that for L > 25 nm, the extracted defect densities are independent of temperature, as expected. However, for L < 25 nm, the plasmons in the highly doped source and drain regions prevail over neutral defects. Further measured degradation in the virtual source velocity at saturation matches that of full Coulomb Monte Carlo simulation, for the first time experimentally confirming S/D plasmons as the dominant mechanism for L < 25 nm.
Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM
(2012)
Tsai, Ming-Fu
;
Tsai, Jen-Huan
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with sigma(offset) reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.