Browsing by Author "Tsai, Ping-Yuan"

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A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
(2018-11-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
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Yen, Ting-Yang
A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 mu V-rms and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5-3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18-mu m CMOS technology and occupies 25 mm(2). Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.
A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control
(2017-01-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
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Yen, Ting-Yang
This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5-3mA biphasic current stimulation. The SoC is powered wirelessly and bidirectional data telemetry is realized through the same pair of coils in 13.56MHz.
A LOW-POWER ALL-DIGITAL PHASE MODULATOR PAIR FOR LINC TRANSMITTERS
(2011)
Tsai, Ping-Yuan
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Chen, Tsan-Wen
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power all-digital phase modulator (PM) pair to generate constant-envelope signals for LINC transmitters. To reduce the power overhead, an open-loop delay line based phase shifter with a continuous locking scheme is adopted for the PM design. This design is implemented by 90 nm CMOS technology with active area of 0.1892 mm(2). The PM provides 8-bit resolution with RMS error 0.33 degrees at IF frequency 80 MHz, and the power consumption is only 885 uW with 1.0 V supply voltage. Considering a 64-QAM OFDM system, the EVM of -31.87 dB can be achieved by using the proposed PM pair.
A QPSK/16-QAM OFDM-based 29.1Mbps LINC Transmitter for Body Channel Communication
(2012)
Tsai, Ping-Yuan
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Hsu, Shu-Yu
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Chang, Jen-Shin
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Chen, Tsan-Wen
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Lee, Chen-Yi
This paper proposed a high speed Body Channel Communication (BCC) transmitter under IF 20MHz, adopting the OFDM modulation and uneven multi-level LINC technique to reduce the power and complexity of the front-end circuit. The OFDM uses 16-QAM modulation to enhance the data rate and could select to use a convolutional code to increase the coding gain. The phase modulator in the LInear amplification with Nonlinear Component (LINC) transmitter uses not only clock-gating scheme but also the glitch free protection. A detection and calibration DSP are also integrated to solve the LINC branch mismatch problem. Finally the capacitive sensing circuit provides the information of the connectivity between pastes and human. The chip is implemented by 90nm CMOS process, with die area 1.3mm(2). The maximum data rate could achieve 29.1Mbps. The total power is 1.925mW, resulting in 0.07nJ/bit transmission energy and 2.92 bps/Hz spectral efficiency.
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
(2011-11-01)
Chen, Tsan-Wen
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Tsai, Ping-Yuan
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Yu, Jui-Yuan
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Lee, Chen-Yi
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電機工程學系
Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm(2). The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34 degrees). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 mu W which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15 degrees phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10 degrees phase mismatch, the system EVM of -29.81 dB and ACPR of -34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.
An Energy-Efficient OFDM-Based Baseband Transceiver Design for Ubiquitous Healthcare Monitoring Applications
(2011)
Shih, Tzu-Chun
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Chen, Tsan-Wen
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Sung, Wei-Hao
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Tsai, Ping-Yuan
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Lee, Chen-Yi
This work proposes an orthogonal frequency division multiplexing (OFDM) based baseband transceiver design for wireless body area network (WBAN) application. Based on the analysis of the WBAN operation behavior, high transmission data rate and low power implementation techniques are proposed to reduce the transmission energy. An electrocardiography (ECG) transmission platform is also established with proposed design for system evaluation. This chip is implemented in a 90nm CMOS technology with the core size of 2.85 mm(2), and this baseband transceiver dissipates 357.14 uW with supply voltage 0.5 V. The proposed chip provides maximum 9.7 Mbps data rate, resulting in active duty cycle of 0.1763% and the transmission energy of 0.37 nJ / bit.
An OFDM-based 29.1Mbps 0.22nJ/bit Body Channel Communication Baseband Transceiver
(2015)
Tsai, Ping-Yuan
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Chang, Yu-Yun
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Hsu, Shu-Yu
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Lee, Chen-Yi
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電機學院
This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and ( 2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes -high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm(2) chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.