Browsing by Author "Tsai, Shang-Jen"

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A Latency-Elastic and Fault-Tolerant Cache for Improving Performance and Reliability on Low Voltage Operation
(2015)
Yu, Yung-Hui
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Wang, Po-Han
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Tsai, Shang-Jen
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Chen, Tien-Fu
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資訊工程學系
The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
(2016-06)
Wang, Po-Hao
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Tsai, Shang-Jen
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Tanjung, Rizal
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. (C) 2016 Elsevier B.V. All rights reserved.
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
(2017-12-01)
Wang, Po-Hao
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Chien, Yung-Chen
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Tsai, Shang-Jen
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Lin, Xuan-Yu
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Tanjung, Rizal
An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The poor performance of an ultralow-voltage core causes most workload requirements to awaken and then execute on the host core, leading to high energy consumption. In this paper, we propose a ULV-Turbo cache based on a ULV-selective-ally 8T static random access memory (SRAM) that is able to perform reliable ultralow-voltage operation and provide the speedup function of SRAM rows ally. The system is able to speed up the ULV core instantaneously and execute more applications with the ULV-Turbo cache. In our system-wide evaluation based on a real attitude and heading reference system workload on an asymmetric wearable system, the ULV-Turbo cache reduces the energy consumption of the entire system by approximately 36%.