Browsing by Author "Tsai, Shiang-Yu"

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Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
(2012-09-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.
Design of ESD Protection Cell for Dual-Band RF Applications in a 65-nm CMOS Process
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
An ESD protection cell consisted of a diode, a silicon-controlled rectifier (SCR), a PMOS, and inductors was proposed for dual-band radio-frequency (RF) ESD protection. The proposed ESD protection cell was suitable for RF circuit designers for them to easily apply ESD protection in the dual-band RF circuits.
Design of ESD Protection for RF CMOS Power Amplifier with Inductor in Matching Network
(2012)
Tsai, Shiang-Yu
;
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
Due to the potential for mass production, CMOS technologies have been widely used to implement radio-frequency integrated circuits (RF ICs). Electrostatic discharge (ESD), which is one of the most important reliability issues in CMOS technologies, must be considered in RF ICs. In this work, an on-chip ESD protection design for RF power amplifier (PA) was presented. The ESD protection design consisted of an inductor in the matching network of PA. The PA with this ESD protection had been designed and fabricated in a 65-nm CMOS process. The ESD-protected PA can sustain over 4-kV human-body-mode (HBM) ESD stress, while the unprotected PA was degrated after 1-kv HBM ESD stress.
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
(2013-01-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.