Browsing by Author "Tsai, Tsung-Yen"

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120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Magnetic Power Monitoring and Harvesting System
(2015-04-01)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Kang, Yu-Chai
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Peng, Ruei-Hong
;
Chen, Ke-Horng
The magnetic energy harvesting (MEH) circuit and the power monitoring system are proposed in this paper to enlarge the system sustainability on wireless sensing or the monitoring system. The proposed MEH circuit harvests magnetic power on power wires through a power sensing current transformer (CT) and charges power monitoring system. The MEH circuit includes the direct ac-dc rectifier and the maximum power extracting (MPE) control circuit. The direct ac-dc rectifier can directly rectify ac input to the dc output current. The proposed MPE control fits the characteristic of magnetic energy source compared to the conventional resistor emulation maximum power point tracking method. Owing to continuous tracking the maximum power of the CT, 120% harvesting power improvement can be achieved under the same CT\'s sensing current. Peak efficiency of 82% can be achieved under the sensing current of 8 A. The test chip is fabricated in 0.25 mu m CMOS process with an active area of 0.98 mm(2).
120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
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Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
200nA Low Quiescent Current Deep-Standby Mode in 28nm DC-DC Buck Converter for Active Implantable Medical Devices
(2015)
Chu, Li-Cheng
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Yang, Te-Fu
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Huang, Ru-Yu
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Su, Yi-Ping
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Lin, Chiun-He
the proposed deep-standby mode (DSM) is used in 28nm power management unit (PMU) for long-term usage in active implantable medical devices (AIMD). The PMU can upgrade its normal mode with the proposed embedded auto-cancellation (EAC) technique in order to have high accuracy even if the battery is aging and the PVT variations occur. The test chip fabricated in 28nm CMOS process features low quiescent current of 200nA and output voltage accuracy of 98%. Seamless transition among the DSM and the accurate mode demonstrates both low quiescent current and high accuracy can be achieved in the proposed PMU.
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
(2015-01-01)
Su, Yi-Ping
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Lin, Chiun-He
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Peng, Shen-Yu
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Huang, Ru-Yu
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Yang, Te-Fu
93% Efficiency and 0.99 Power Factor in Pseudo-linear LED Driver
(2016-01-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Chuang, Kai-Cheng
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Yang, Wen-Hau
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Chen, Ke-Horng
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5 mu m 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
95% Light-load Efficiency Single-Inductor Dual-Output DC-DC Buck Converter with Synthesized Waveform Control Technique for USB Type-C
(2016)
Yang, Wen-Hau
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Lin, Chiun-He
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 520V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400 mu m*1350 mu m.
99% High Accuracy Knee Voltage Detection for Primary-side Control in Flyback Converter
(2015)
Tsai, Tsung-Hsun
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Chen, Ke-Horng
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Tsai, Tsung-Yen
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Lin, Jian-Ru
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Lin, Ying-Hsi
this paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5 mu m BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won\'t happen and thus the output ripple can be kept low.
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
(2015-01-01)
Chiu, Chao-Chang
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Huang, Po-Hsien
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Lin, Moris
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Chen, Ke-Horng
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Lin, Ying-Hsi
The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
A 20MHz Low Dropout Controlled Current Sensor for Constant On-Time Based Envelop Tacking Supply Modulator for Radio Frequency Power Amplifier
(2018-01-01)
Lin, Wei-Ting
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Lin, Zong-Yi
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Liu, Chia-Hao
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Chen, Ke-Horng
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Lin, Ying-Hsi
this paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18 mu m CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.
A 20MS/s Buck/Boost Supply Modulator for Envelope Tracking Applications with Direct Digital Interface
(2014)
Yang, Shang-Hsien
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Wey, Chin-Long
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Chen, Jing-Jia
a buck/boost supply modulator (BBSM) is proposed for 4G LTE RF power amplifier (RF-PA) envelope tracking applications. The H-bridges used in non-inverting buck/boost converters are metamorphosed into the current sources and switches of a 4-bit current-steering DAC-like supply modulator. Fast tracking speed is achieved through its inherent open-loop topology, while the direct digital interface provides easy control and integration with digital LTE baseband SoCs. The proposed BBSM is capable of delivering peak power of 2.8W at 20MS/s, with a peak efficiency of 75 %.
A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
(2019-05-01)
Huang, Chao-Jen
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Lai, Yan-Jiun
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Yang, Yu-Jheng Ou
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Chen, Hung-Wei
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Kuo, Chun-Chieh
State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
A 96%-Efficiency and 0.5%-Current-CrossRegulation Single-Inductor Multiple Floating-Output LED Driver with 24b Color Resolution
(2016)
Yang, Hsiang-An
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Yang, Wen-Hau
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers
(2019-11-01)
Muniandi, Balakumar
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Huang, Chao-Jen
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Kuo, Chun-Chieh
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Yang, Te-Fu
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Chen, Ke-Horng
In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58 & x0025; when the charger operates in the turbo boost mode, and achieves 97 & x0025; maximum efficiency when the charger operates in buck charge mode.
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction
(2016-09)
Yang, Shang-Hsien
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Meng, Che-Hao
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Ke-Horng
A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation ((PSCM)-C-2), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-mu m Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.
A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power Amplifiers
(2019-01-01)
Kumari, Neha
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Yang, Shang-Hsien
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Lin, Shian-Ru
In this paper, the switched -capacitor boost (SCB) mode envelope tracking (ET) technique with a switched-capacitor circuit and a low dropout (LDO) regulator are used to replace conventional envelope tracking regulators. At a Peak-to-Average Power Ratio (PAPR) of 7.7dB common for LTE communication, the efficiency is 72%, which is 4% higher than the theoretical limit of conventional ET techniques. When PAPR increases from 6.1dB to 7.3dB, the conventional ET efficiency decreases from 82% to 69% whereas the SCB mode increases by 2%.
A Constant-on-Time Control DC-DC Buck Converter With the Pseudowave Tracking Technique for Regulation Accuracy and Load Transient Enhancement
(2018-07-01)
Yang, Wen-Hau
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Huang, Chao-Jen
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Huang, Han-Hsiang
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Lin, Wei-Ting
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Chen, Ke-Horng
Constant-on-time (COT) control with an additional current feedback path in conventional buck converters can remove the need of large equivalent series resistance (ESR) at the output capacitor but it induces degraded output voltage regulation accuracy and slow transient response owing to opposite reaction between the output voltage and the additional current feedback information. Therefore, this paper proposes the pseudowave tracking (PWT) technique to reduce the load-dependent dc offset voltage of output load regulation while keeping the fast transient response similar to conventional COT buck converter with large ESR. The PWT technique further improves the transient response instantly by extending on-time and off-time periods during light-to-heavy and heavy-to-light load changes, respectively. The test chip fabricated in 28 nm CMOS process has demonstrated the improvement of offset voltage from 42 to 4 mV, while the transient response can be improved to 4 and 5 mu s with load changes from 0.3 to 1.7 A and vice versa, respectively.
A Digital Low-Dropout-Regulator with Steady-State Load Current (SLC) Estimator and Dynamic Gain Scaling (DGS) Control
(2016)
Lin, Jian-He
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Tsou, Wen-Jie
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Chen, Ke-Horng
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Wey, Chin-Long
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Lin, Ying-Hsi
conventional digital low dropout (D-LDO) regulator usually suffers from the drawback of long settling time during transient response due to the usage of shift register architecture. In this paper, the proposed D-LDO regulator can observe the output voltage variations during load transient time to predict the load current for fast transient response. Near optimum turn on power MOSFET in steady state can be derived by the proposed steady-state load current (SLC) estimator while the dynamic gain scaling (DGS) technique can improve transient response and avoid limiting cycle oscillation (LCO) problem. Test chip was designed in 0.18 mu m CMOS process. Simulation results showed the transient response time can be reduced by 88% from 920ns to 115ns.
A Digital Reverse Current Self-calibration Technique in 90% High Efficiency Rectified Power Supply for Near Field Communication through Magnetic Field Induction
(2017-01-01)
Lin, Li-Chi
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Chen, Kuan-Yu
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Yang, Wen-Hau
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Huang, Ru-Yu
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Chen, Ke-Horng
it is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25 mu m CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.
A Digital-Type GaN Driver with Current-Pulse-Balancer Technique Achieving Sub-Nanosecond Current Pulse Width for High-Resolution and Dynamic Effective Range LiDAR System
(2019-01-01)
Ma, Yu-Sheng
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Lin, Zong-Yi
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Lin, Yen-Ting
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Lee, Cheng-Yen
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Huang, Tzu-Ping
A Direct AC-DC and DC-DC Cross-Source Energy Harvesting Circuit with Analog Iterating-Based MPPT Technique with 72.5% Conversion Efficiency and 94.6% Tracking Efficiency
(2016-08)
Chen, Shin-Hao
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Huang, Tzu-Chi
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Ng, Shao Siang
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Lin, Kuei-Liang
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Du, Ming-Jhe
The proposed cross-source energy (CSE) harvesting system accepts universal energy sources, including the ac and dc sources. The buck-boost conversion of CSE automatically converts ac or dc input into dc output without being limited by the type of universal energy source. The CSE technique simultaneously supplies the regulated output for the system loading and the battery charging output. A test chip fabricated in the VIS Bipolar, CMOS, and DMOS (BCD) process can optimally derive harvest energy with 72.5% power efficiency when one solar input source is used. A backup converter is designed to complement the CSE technique to guarantee the regulation of output voltage. The proposed analog iterating-based (AIB) maximum power point tracking (MPPT) technique achieves 94.6% tracking efficiency without complex data calculation and storage, which are better results compared with those of previous research.