Browsing by Author "Tsai, Tsung-Ying"

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A Fully Tunable Two-Pole Bandpass Filter
(2015-05-01)
Chi, Pei-Ling
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Yang, Tao
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Tsai, Tsung-Ying
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
In this letter, a two-pole tunable combline filter that allows for operational agility of the center frequency, passband bandwidth, and locations of upper and lower transmission zeros is proposed. To increase the tunable range of constant absolute-bandwidth for all frequency tuning states, a novel T-type bandwidth-control network was devised between resonators to flexibly tune the coupling coefficient without limitations imposed by the available varactor capacitance. By use of tunable source-load coupling, two tunable transmission zeros were produced on both sides of the passband to significantly improve filter selectivity and to dynamically afford interference suppression. A second-order 1.7-2.7 GHz filter with 1 dB constant bandwidth tuning from 50 to 110 MHz and transmission zero locations tuning from 300 to 700 MHz with respect to the passband was developed and fabricated. Good agreement was obtained between the simulated and experimental results.
Effect of fractal parameters on optical properties of cold rolled aluminum alloy strips with induced surface deflection: Simulations and experimental correlations
(2020-05-01)
Mahmood, Muhammad Arif
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Tsai, Tsung-Ying
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Hwu, Yhu-Jen
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Lin, Wei-, Jr.
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Liu, Lee-Cheng
Cold rollings for Al5182 aluminum alloy strips are carried out to evaluate the optical parameters with the applications of two lubricants and various operating conditions. In order to obtain these optical parameters, the fractal parameters which includes periodic lengths (L-x, L-y) and fractal dimensions (D-x, D-y) in the modified three-dimensional formula for the fractal surface morphology have been solved first for the rolled surfaces. This three-dimensional formula can provide an effective way to correlate these fractal parameters with the optical parameters using TracePro software, which can help to define rolling conditions efficiently for the specific demand of optical properties. The deterministic results for fractal surface simulations using MATLAB in series and 20 incident angle simulation in TracePro software explain that an increase in D-x and D-y will yield dense profiles which elevates the maximum illuminance and lower down the minimum illuminance. While an increment in L-x and L-y would increase the characteristic distance between two predominant asperities and increase minimum illuminance and decrease maximum illuminance. Finite element analyses prove that different friction coefficients in the upper and lower rolls potentially induce surface deflection and thus affect the optical properties. A high illuminance uniformity can be achieved by making a compromise among the fractal parameters (D-x, D-y, L-x and L-y) such that a small difference in the maximum and minimum illuminances is available.
Escaped Boundary Pins Routing for High-Speed Boards
(2013-03-01)
Chin, Ching-Yu
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Kuan, Chung-Yi
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Tsai, Tsung-Ying
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Chen, Hung-Ming
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Kajitani, Yoji
Routing for high-speed boards is still achieved manually today. There have recently been some related works to solve this problem; however, a more practical problem has not been addressed. Usually, the packages or components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. In this paper, we describe this fixed ordering boundary pin routing problem, and propose a practical approach to solve it. Not only do we provide a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. Our approach has different features compared with the conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirements and wire shape resemblance for high-speed signal routes on board. Our results show that we can utilize routing resources very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board buses as well.
On Routing Fixed Escaped Boundary Pins for High Speed Boards
(2011-01-01)
Tsai, Tsung-Ying
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Lee, Ren-Jie
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Chin, Ching-Yu
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Kuan, Chung-Yi
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Chen, Hung-Ming
Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the pack-ages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. Previous works in escape routing are not likely to be used due to this nature, in this work, we describe this fixed ordering boundary pin escaping problem, and propose a practical approach to solve it. Not only can we have a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. our approach has different feature compared with conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirement and wire shape resemblance for high speed signal routes on board. Our results show that we can utilize routing resource very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board busses as well.
Testing Methods for Detecting Stuck-open Power Switches in Coarse-Grain MTCMOS Designs
(2010)
Mu, Szu-Pang
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Wang, Yi-Ming
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Yang, Hao-Yu
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Chao, Mango C. -T.
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Chen, Shi-Hao
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods.