Browsing by Author "Tsai, Tu-Hsiung"

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Cost-Effective Decap Selection for Beyond Die Power Integrity
(2014-01-01)
Chen, Yi-En
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Tsai, Tu-Hsiung
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Chen, Shi-Hao
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Chen, Hung-Ming
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電子工程學系及電子研究所
In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficient methodology "PDC-PSO" to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.
Path-Based Cell Flipping Optimization for Wirelength Reduction and Routability
(2010)
Shih, Ying-An
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Tsai, Tu-Hsiung
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Wirelength reduction is always a concern in almost every methodology in physical design optimization. A recent study shows that solving cell flipping optimally can further reduce wirelength without affecting the original placement solution. In practical observation, there are still a lot of placed standard 2-pin logic cells which can be further mirrored to decrease the total routing length. In this work, we provide a path-based optimization methodology that can be applied before detailed routing, and this will help the router to improve the final routing length. This method can also be easily applied in the ECO stage to prevent the wire crossing effects, without impacting the local routability. A number of real industry tape-out cases are experimented to illustrate the effectiveness of the proposed methodology and to get shorter wirelength.
Routability-Driven Bump Assignment for Chip-Package Co-Design
(2014-01-01)
Chen, Meng-Ling
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Tsai, Tu-Hsiung
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Chen, Hung-Ming
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Chen, Shi-Hao
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電子工程學系及電子研究所
In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.