Browsing by Author "Tsai, W. J."

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Insight of stress effect on the ONO stack layer in a SONOS-type flash memory cell
(2006)
Yeh, C. C.
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Liao, Y. Y.
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Wang, Tahui
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Tsai, W. J.
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Lu, T. C.
The stress effect on the ONO stack layer in a two-bit SONOS-type memory cell is investigated. Our results show that P/E cycles induced stress will generate extra nitride, oxide, and interface traps in the ONO stack layer. Besides, these stress created traps are unstable and will be annealed by additional thermal treatment. Storage electrons escape from stress-created nitride and oxide traps and the trap annealing effects are root causes of charge loss in a SONOS cell.
Investigation of charge loss in cycled NBit cells via field and temperature accelerations
(2006)
Tsai, W. J.
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Zous, N. K.
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Chen, H. Y.
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Liu, Lenvis
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Yeh, C. C.
In nitride storage flash memories, the high-V-T state retention loss induced by field and temperature acceleration is compared between single cells and products. Our result reveals that the charge loss path is the same no matter which accelerating methods is used. The traps created at the bottom oxide during P/E cycling provide such leak paths. In addition, the annealing of interface states would play a role in the V-T loss during high-temperature bake.
Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
(2018-01-01)
Liu, Y. H.
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Lin, H. Y.
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Jiang, C. M.
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Wang, Tahui
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Tsai, W. J.
Data pattern effects on nitride charge lateral migration and V-t retention loss in a charge trap flash memory is investigated. We use channel hot electron program and band-to-band tunneling hot hole erase to inject different amounts of electrons and holes at the two sides of a channel in a SONOS cell. An interface oxide trap near an injected charge packet and its associated random telegraph signal (RTS) are used as an internal probe to detect a local channel potential change resulting from trapped charge lateral migration. Vt retention loss and RTS in various charge storage patterns are characterized and analyzed. At a similar built-in electric field, nitride trapped holes are found to be more mobile than trapped electrons in lateral migration.
Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String
(2016-08)
Chou, Y. L.
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Wang, Tahui
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Lin, Mercator
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Chang, Y. W.
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Liu, Lenvis
We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.