Browsing by Author "Tsai, Wei-Lun"

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A Low-Complexity Mixed-Radix FFT Rotator Architecture
(2018-01-01)
Tsai, Wei-Lun
;
Chen, Sau-Gee
;
Huang, Shen-Jui
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
FFT-based OFDM and SC-FDMA transmission technologies have been widely adopted in most advanced telecommunication systems. For future 5G mobile communication systems, FFT again is expected to play very crucial roles. As such, design of FFT processors with unprecedentedly high performance has become a hard challenging problem that must be overcome. Among the components of an FFT processor, the rotator composed of ROMs and multipliers for twiddle factor multiplications take up the most area and power consumption. In order to reduce the cost, a reconfigurable multiplier-less and ROM-less rotator design approach is proposed in this paper. This approach supports both power-of-two and non-power-of-two FFT lengths. It effectively reduces the area by applying a series of decomposition and sharing schemes. An example of a rotator supporting 128-2048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm CMOS technology. Compared to the existing design, this work has 16.75% area reduction and 62.94% power reduction.
Reconfigurable Radix-2(k)x3 Feedforward FFT Architectures
(2019-01-01)
Tsai, Wei-Lun
;
Chen, Sau-Gee
;
Huang, Shen-Jui
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to the increasing demand for high-throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi-length FFT processor with the requirement meet has become unprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed-radix 2(k)x3-point feedforward FFT architectures are proposed. It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 1282048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation.