Browsing by Author "Tsai, Wen-Jer"

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A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport
(2009-02-01)
Wang, Tahui
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Tang, Chun-Jung
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Li, C. -W.
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Lee, Chih Hsiung
;
Ou, T. -F
We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an n(+) BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a V(ds) of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method
(2017-07-17)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Lin, Hsiao-Yi
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Wang, Tahui
;
Tsai, Wen-Jer
We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport. Published by AIP Publishing.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
;
Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
(2017-01)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Chen, Wei-Chun
;
Wang, Tahui
;
Tsai, Wen-Jer
We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
(2017-01)
Liu, Yu-Heng
;
Jiang, Cheng-Min
;
Chen, Wei-Chun
;
Wang, Tahui
;
Tsai, Wen-Jer
We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
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Cheng, C. H.
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Lee, C. W.
;
Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String
(2019-04-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Ku, S. H.
;
Liu, Lenvis
Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 mu s or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in "pseudo" charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
(2019-01-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Lu, Chun-Chang
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Ku, S. H.
We investigate a hot-carrier injection- induced program disturb in a 3D NAND flash memory. As there exist specific coding patterns, a "down-coupling" region and a "pre-charge" regions are formed during program-verify and the following program phases, respectively, in the inhibit cell strings. A high heating field is built nearby the PGM wordline. Hot carriers may inject into the inhibit cells as Vpgm is applied. Soft ramp-down and pre-turn-on schemes are proposed to mitigate this disturb.
Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on ${V}_{{t}}$ Retention Loss in a Multilevel Charge Trap Flash Memory
(2019-12-01)
Liu, Yu-Heng
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Zhan, Ting-Chien
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Wang, Tahui
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Tsai, Wen-Jer
;
Lu, Tao-Cheng
We investigate electron and hole lateral migration in retention loss in a multilevel charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that retention loss in a program state exhibits a turnaround characteristic as program level increases. loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and loss is dominated by electron vertical loss and lateral migration.
Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String
(2016-01-01)
Tsai, Wen-Jer
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Lin, W. L.
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Cheng, C. C.
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Ku, S. H.
;
Chou, Y. L.
Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.