Browsing by Author "Tsai, Yueh-Lin"

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Reflection characteristics of a composite planar AMC surface
(2012-03-01)
Hwang, Ruey-Bing
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Tsai, Yueh-Lin
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電機工程學系
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Department of Electrical and Computer Engineering
This study investigates the reflection characteristics of a composite Artificial Magnetic Conductor (AMC) surface consisting of multiple orthogonal gradient AMC surfaces arranged in a two-dimensional periodic pattern. The gradient AMC surface in this study consists of square metal patches of variable size printed on a grounded dielectric substrate. Due to the orthogonal placement of the gradient AMC surface, the incident energy of a plane wave normally incident on the composite AMC surface will be reflected into four major lobes away from the impinging direction. To achieve a systematical design, a simple formula based on array antenna theory was developed to determine the reflection pattern of the gradient AMC surface illuminated by a normal incident plane wave. A time-domain full-wave simulation was also carried out to calculate the electromagnetic fields in the structure and the far-field patterns. The scattering patterns of the structure were measured in an electromagnetic anechoic chamber. Results confirm the design principle and procedures in this research. Since such a composite AMC surface can be easily fabricated using the standard printed circuit board technique without via-hole process, it may have potential applications in beam-steering and radar cross section reduction. Copyright 2012 Author(s). This article is distributed under a Creative Commons Attribution 3.0 Unported License. [doi: 10.1063/1.3682352]
Study on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistors
(2020-04-01)
Chang, You-Tai
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Tsai, Yueh-Lin
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Peng, Kang-Ping
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Su, Chun-Jung
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Li, Pei-Wen
In this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physics
Time-Division Multiplexing Monopulse Antenna System for DVB-SH Application
(2015-02-01)
Tsai, Yueh-Lin
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Hwang, Ruey-Bing
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電機學院
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College of Electrical and Computer Engineering
This study involved developing a time-division multiplexing monopulse antenna system for tracking the DVB-SH signal operated in S-band. Such a system consists of a mode-former circuit and a stacked circularly polarized antenna array, which was implemented using planar-printed circuit technology. In the mode-former circuit, a four-way power splitter comprising Wilkinson power dividers and four switched-line phase shifters were employed to provide 0 degrees/180 degrees phase angles at each output port. The sum-and-difference angle discriminators were implemented along vertical and horizontal planes for detecting the incident elevation and azimuth angles. The stacked circularly polarized antenna array, composed of four edge-fed patches on the bottom layer and four corresponding parasitic patches, were exploited on the top layer to increase the axial ratio bandwidth. The experimental results revealed that, at 2.185 GHz, the null depth of the difference patterns were -34.2 dB and -33.2 dB along the two principal planes.
Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor
(2020-01-01)
Change, You-Tai
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Tsai, Yueh-Lin
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Peng, Kang-Ping
;
Su, Chun-Jung
;
Li, Pei-Wen
In this article, we investigate the four-level random telegraph noise (RTN) characteristics of a gate-all-around (GAA) nanowire (NW) transistor. The RTN-testing devices were fabricated with the sidewall spacer etching technique. The effective channel length and width are approximately 150 and 30 nm, respectively. By decoupling the four-level RTN, we are able to extract the time constants associated with the two traps. Circle-shaped approximations are used to mimic the triangular NW for evaluating the depths of the traps. The extracted depths of the two traps are very close to each other, which is consistent with the time-evolution measured results. We've also explored the probabilities of transitions between two specific current levels in the RTN characteristics, as well as the relative trapping/de-trapping frequencies.