Browsing by Author "Tsao, Yu-Ching"

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A Dual-Gate InGaZnO4-Based Thin-Film Transistor for High-Sensitivity UV Detection
(2019-08-01)
Chen, Po-Hsun
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Tsao, Yu-Ching
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Chien, Yu-Chieh
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Chiang, Hsiao-Cheng
;
Chen, Hua-Mao
UV-sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV-sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV-light-sensing properties of an amorphous InGaZnO4 (IGZO) thin-film transistor with a dual-gate structure and relatively small device size (width/length = 50 mu m/10 mu m) that achieves high sensitivity through a threshold-voltage-(V-th)-adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10(6). Furthermore, the UV sensitivity of the dual-gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual-gate a-IGZO transistor to be used for high-performance UV sensing while being effectively integrated in display applications.
Abnormal C-V Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs
(2019-11-01)
Huang, Shin-Ping
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Chen, Po-Hsun
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Tsao, Yu-Ching
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Chen, Hong-Chih
;
Zheng, Yu-Zhe
We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.
Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors
(2017-01-09)
Tsao, Yu-Ching
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chiang, Hsiao-Cheng
This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. Published by AIP Publishing.
Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors
(2020-09-30)
Tu, Hong-Yi
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Chang, Ting-Chang
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Tsao, Yu-Ching
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Tai, Mao-Chou
;
Tsai, Yu-Lin
Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.
Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes
(2019-11-01)
Tu, Hong-Yi
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Tsao, Yu-Ching
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Tai, Mao-Chou
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Chang, Ting-Chang
;
Tsai, Yu-Lin
This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.
Effect of a-InGaZnO TFT Channel Thickness under Self-Heating Stress
(2019-09-18)
Tai, Mao-Chou
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Chang, Po-Wen
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Chang, Ting-Chang
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Tsao, Yu-Ching
;
Tsai, Yu-Lin
In this work, indium-gallium-zinc-oxide thin film transistors (IGZO-TFTs) with different channel thicknesses were compared after self-heating stress (SHS). Although TFTs with a thicker channel have higher current during stress conditions, less degradation is reported. This degradation, manifest as the threshold voltage shift in the transfer characteristics, is well described by the stretched-exponential equation. In addition, the average effective barrier height, Et, is extracted to compare the difference in degradation between both TFTs, and finds that the barrier height in the thick channel device is twice that of the thin channel device. Finally, a COMSOL simulation is performed to demonstrate the electrical difference at the gate insulator layer and confirm such phenomena. (C) 2019 The Electrochemical Society.
Impact of Dehydrogenation Annealing Process Temperature on Reliability of Polycrystalline Silicon Thin Film Transistors
(2019-10-01)
Huang, Shin-Ping
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Chen, Po-Hsun
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Chen, Hong-Chih
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Zheng, Yu-Zhe
;
Chu, Ann-Kuo
This letter investigates variations in polycrystalline silicon thin film transistor (TFT) performance under illumination and negative bias temperature instability (NBTI) tests due to different dehydrogenation annealing temperatures during the fabrication process. The depth of the density of state (DOS) in polysilicon can be indirectly determined by the TFT response to light illumination, since dangling bonds act as recombination centers. The electrical characteristics of TFTs after undergoing NBTI can also be indicative of the bonding type of silicon atoms. By analyzing the results of these reliability tests, the type of DOS can be clarified, which is beneficial for realizing the relationship between performance and reliability.
Improving Reliability of High-Performance Ultraviolet Sensor in a-InGaZnO Thin-Film Transistors
(2019-09-01)
Tsai, Yu-Lin
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Chien, Yu-Chieh
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Chang, Ting-Chang
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Tsao, Yu-Ching
;
Tai, Mao-Chou
High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect I-ON/I-OFF ratio up to 10(6) and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.
Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
(2020-09-01)
Lin, Chih-Chih
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Tai, Mao-Chou
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Chang, Ting-Chang
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Tsao, Yu-Ching
;
Wang, Yu-Xuan
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.
Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors
(2017-09-25)
Chiang, Hsiao-Cheng
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Chang, Ting-Chang
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Liao, Po-Yung
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Chen, Bo-Wei
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Tsao, Yu-Ching
This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (I-on) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis. Published by AIP Publishing.
Investigation of the Capacitance-Voltage Electrical Characteristics of Thin-Film Transistors Caused by Hydrogen Diffusion under Negative Bias Stress in a Moist Environment
(2019-10-30)
Chen, Hong-Chih
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Kuo, Chuan-Wei
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Chang, Ting-Chang
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Lai, Wei-Chih
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Chen, Po-Hsun
In this study, the impact of moisture on the electrical characteristics of an amorphous In-Ga-Zn-O thin-film transistor (a-IGZO TFT) was investigated. In commercial applications of such TFTs, high stability and quality performance in humid environments are essential. During TFT operation under ambient moisture, the electrolysis of water molecules occurs via the tip electric field effect. Hydrogen diffuses from the etch-stop layer or back-channel into the main channel under a negative electric field. The hydrogen atoms act as shallow donors (which causes the carrier concentration in the channel to rise), causing the threshold voltage (V-TH) to shift in the negative direction. Hydrogen diffusion from the overlap of the source/drain and gate electrodes to the channel center caused by the tip electric field induces a significant barrier lowering and V-TH shifts in a short-channel device. However, under negative bias stress (NBS) in ambient moisture, the negative V-TH shift is more obvious in short- than in long-channel devices, indicating suppressed hydrogen diffusion in long-channel devices. This is attributed to the electrolysis of water by the tip electric field at the source, drain, and gate electrodes, which causes hydrogen to diffuse to the center of the channel. Here, a novel physical model of the capacitance-voltage (C-V) electrical property changes under ambient moisture is proposed, based on the early appearance of abnormalities in the C-V measurements. The electrolysis of water caused by the tip electric field and electrical abnormalities caused by hydrogen diffusion into the a-IGZO active layer are explained by this model. A secondary-ion mass spectrometry analysis shows that hydrogen content in the channel generally increases under NBS in ambient moisture. The degradation behavior due to moisture in a-IGZO is clarified. Thus, inhibiting the tip electric field may benefit future flexible-display and gas-sensing applications.
Role of H2O Molecules in Passivation Layer of a-InGaZnO Thin Film Transistors
(2017-04-01)
Chien, Yu-Chieh
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Chang, Ting-Chang
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Chiang, Hsiao-Cheng
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Chen, Hua-Mao
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Tsao, Yu-Ching
This letter analyzes performance and reliability of inverted staggered type amorphous indium-gallium-zinc oxide devices in a moist environment with H2O molecules in the passivation layer. There is a negative threshold voltage shift (Delta Vth) in the saturation region (V-D = 10 V), which increases with decreasing channel length. We propose that this is explained by the drain-induced barrier lowering that is due to the H2O molecules. Moreover, a hydrogen bonding model under bias stress is also proposed, in contrast to the conventional H2O doping model. Recovery behavior after bias stress and ac operation were utilized to distinguish the difference between these models.