Browsing by Author "Tseng, Chi-Yao"

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A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization
(2008)
Wei, Ting-Chen
;
Liu, Wei-Chang
;
Tseng, Chi-Yao
;
Long, Syu-Siang
;
Jou, Shyh-Jye
An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and +/- 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment The total memory requirement of this chip is 102.8KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mu m CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600 mu m x 3600 mu m.
Low Complexity Synchronization Design of an OFDM Receiver for DVB-T/H
(2009-05-01)
Wei, Ting-Chen
;
Liu, Wei-Chang
;
Tseng, Chi-Yao
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
In this paper, an OFDM baseband receiver for DVB-T/H is presented. The receiver contains four synchronizations, an OFDM symbol synchronization, a carrier synchronization, a sampling clock synchronization and a scattered pilots synchronization. This paper proposes several novel designs to reduce the synchronization latency and hardware complexity. The carrier and clock synchronization loops are fully digitalized schemes. The scattered pilots synchronization adopts a two stages scheme to reduce the detection latency. In addition, the pre-filling scheme reduces the latency of channel estimation. The design result shows that the equivalent gate count is about 810K gates including 102.8KB memory(1).
Low power and power aware design for DVB-T/H baseband inner receiver
(2007)
Tseng, Chi-Yao
;
Wei, Ting-Chen
;
Liu, Wei-Chang
;
Jon, Shyh-Jye
;
電子工程學系及電子研究所
From hardware point of view, system and RTL low power and power aware design techniques are applied to the DVB-T/H baseband inner receiver. In RTL design, we use pre-computation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture so that each block can reduce power from 3% to 26%. In system level, the proposed DPM (Dynamic Power Manager) is a power control unit or our system. When the system enters the offset tracking mode, the DPM controls the power states of system blocks between the GI (Guard Interval) period and symbol period. The power reduction ratio ranges from 3%-20% (it depends on the GI mode). Moreover, a predicted phase scheme is proposed to provide the initial phase offset for the start of symbol period during offset tracking mode. The overall reduction for synchronization loop is about 50% in both hardware area and power.