Browsing by Author "Tseng, Chien-Wei"

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A 60 GHz 19.6 dBm Power Amplifier With 18.3% PAE in 40 nm CMOS
(2015-02-01)
Tseng, Chien-Wei
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Wang, Yu-Jiu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This letter reports a fully integrated 60 GHz power amplifier (PA) implemented in TSMC 40 nm CMOS technology. This PA is based on a three-stage two-way differential topology with an output transformer-based power combining network. This topology improves layout symmetry and mitigates parasitic effects between different signal paths to increase overall efficiency. The use of parasitic coupling capacitors inside a vertically-coupled transformer can increase impedance transformation ratio. This PA achieves 20.3 dB power gain, 19.6 dBm output power with 18.3% peak PAE, and 12 GHz bandwidth.
A Fully-Integrated Ka-Band 4TX/4RX Phased-Array Transceiver IC in 65nm CMOS
(2016)
Chu, Ching-Yun
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Tseng, Shao-Ting
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Gao, Jing-Zhi
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Chen, Yuan-Pu
;
Chang, Yu-Chen
This paper presents a fully-integrated Ka-band 4RX/4TX phased-array transceiver IC. The four transceiver channels are synchronized by an I/Q standing wave oscillator (SWO). Their signal phases are shifted by hybrid analog IF and LO phase interpolators, and can be controlled digitally and independently. The SWO further composes an on-chip PLL, and is locked to a 1.09 GHz off-chip global reference to scale to a large array at board level. Each receiver channel achieves 66 dB maximum conversion gain and 4.4 dB minimum noise figure. Each transmitter channel achieves 18 dBm maximum output power. The chip is mounted on a high-frequency laminate, inside which embedded cables connect its RF pads to Vivaldi antennas also inside the same PCB. With the PCB, each channel achieves 360 degrees phase shifting capability under a maximum calibrated 3.7 degrees phase errors. The PCB module presents successful beam steering with 23 degrees measured four-channel 3-dB beamwidth. This chip consumes a peak 5 W power at transmit mode, and is fabricated in TSMC 65nm CMOS technology with a 4 x 2.5 mm(2) chip area.