Browsing by Author "Tseng, HC"

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Characterization of boron silicide layer deposited by ultrahigh-vacuum chemical-vapor deposition
(1996-11-01)
Tseng, HC
;
Pan, FM
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Deposition of a boron-containing layer using B2H6 diluted with H-2 on a Si(001) surface has been carried out in an ultrahigh-vacuum chemical-vapor-deposition (UHV-CVD) system. The deposited boron-containing layers were characterized by atomic force microscope and Auger electron spectroscopy (AES), and the junction depth was determined by secondary-ion-mass spectroscopy. Effective doping is accomplished before perceivable nucleation is initiated. Islands are first formed on the substrate surface at a small dose of diborane, and the grains coalesce to form a rough him for higher doses. At growth temperature above 800 degrees C, the film is composed of possibly SiB6, according to AES depth profiles. Correlation between the junction depth and the sheet resistance of the UHV-CVD-deposited specimens prepared under various conditions is discussed. Postdeposition rapid thermal annealing was performed to study the effect of subsequent thermal cycles on the junction depth and sheet resistance. (C) 1996 American Institute of Physics.
Effects of isolation materials on facet formation for silicon selective epitaxial growth
(1997-10-20)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, JR
;
Chen, LJ
Effects of isolation materials on facet formation for low temperature Si selective epitaxial growth (SEG) using Si2H6 have been demonstrated by ultrahigh vacuum-chemical molecular epitaxy (UHV-CME) system. The activation energy of the Si epitaxial growth is 47.35 Kcal/mol. The isolation material includes silicon nitride, wet oxide, and tetraethylorthosilicate (TEOS) oxide. Different isolation materials have different faceting behaviors for the Si epilayer. A silicon nitride mask and a wet oxide mask result in a preferred faceting plane of (111) and (311), respectively. Using a TEOS oxide mask, we obtain a low temperature Si SEG layer without facet and twin formation, The preferred faceting plane orientation for different isolation materials is ascribed to the difference in the interface free energy between the Si layer and the isolation material. (C) 1997 American Institute of Physics.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Effects of isolation oxides on undercut formation and electrical characteristics for silicon selective epitaxial growth
(1997-06-01)
Tseng, HC
;
Chang, CY
;
Pan, FM
;
Chen, LP
;
電子工程學系及電子研究所
Three isolation oxide structures have been prepared to study their resistance to the undercut formation during selective epitaxial growth (SEG) processes. The N2O annealed oxide tetraethyoxysilane (TEOS) oxide stacked structure has the best resistance to the undercut formation and exhibits the best electrical characteristics compared to the other two isolation oxide structures prepared in the study, which are a wet oxide and a TEOS oxide. This is ascribed to a smaller interfacial stress between the isolation oxide and the silicon substrate for the stacked structure. The sidewall damage is the predominant factor deteriorating the current-voltage (I-V) characteristics of the N+-P SEG diodes. When treated with a quick HF dip and followed by a low temperature desorption cleaning before the SEG process, the N+-P SEG diode, which has no perceivable undercut, shows satisfactory I-V characteristics.
Extraction of substrate parameters for RF MOSFETs based on four-port measurement
(2005-06-01)
Wu, SD
;
Huang, GW
;
Chen, KM
;
Chang, CY
;
Tseng, HC
In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y-22 can be well modeled up to 26.5 GHZ based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.
Hot-carrier effects on power characteristics of SiGeHBTs
(2004-06-01)
Huang, SY
;
Chen, KM
;
Huang, GW
;
Tseng, HC
;
Hsu, TL
This letter investigates hot-carrier (HQ effects on the power characteristics of Si-SiGe HBTs using load-pull measurements. We found that the output power, power gain, and linearity of Si-SiGe HBTs are degraded after HC stress. Under constant base-current measurement, the HC-induced power performance degradation is found to be much worse than that under constant collector-current measurement. The HC effects on the cutoff frequency, nonlinearity terms of base-current and collector-current, and third-order intermodulation (IM3) cancellation effect have been analyzed to explain the experimental observations.
Hot-carrier induced degradations on RF power characteristics of SiGe heterojunction bipolar transistors
(2004)
Huang, SY
;
Chen, KM
;
Huang, GW
;
Hsu, TL
;
Tseng, HC
Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs were investigated in this paper. We found that the small-signal current gain, output power, and power gain of Si/SiGe HBTs are suffered by the HC stress. With different bias conditions, the degradations of cutoff frequency and output power were found to be worse under constant base-current measurement than that under constant collector-current measurement. These phenomena have been explained by the change of the current gain, transconductance, and base-emitter resistance under stress.
Hot-carrier induced degradations on RF power characteristics of SiGe heterojunction bipolar transistors
(2005-06-01)
Huang, SY
;
Chen, KM
;
Huang, GW
;
Liang, V
;
Tseng, HC
Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs are investigated in this paper. By using the two-tone load-pull measurement, we find that not only the cutoff frequency, but also the output power performances of Si/SiGe HBTs are suffered by the HC stress. In this work, S-parameters and intrinsic elements of an equivalent hybrid-pi model were used to validate the HC effects on high-frequency characteristics. With different bias conditions, the degradations of cutoff frequency, power gain, and linearity are found to be worse under constant base-current measurement than that under constant collector-current measurement. The HC-induced degradations on the current gain, transconductance, and ideality-factor of base and collector currents are analyzed to explain the experimental observations.
Impact of hot carrier stress on RF power characteristics of MOSFETs
(2005)
Huang, SY
;
Chen, KM
;
Huang, GW
;
Yang, DY
;
Chang, CY
This paper investigates hot-carrier (HQ effects on the RF power and linearity characteristics of MOS transistors using load-pull measurement. We found that the RF power characteristics are affected by the HC stress, and the linearity of MOS transistors is clearly degraded after HC stress at constant gate voltage measurement. However, at high gate voltage bias, the HC-induced power degradation is much reduced compared with that under low gate voltage regimes. In addition, HC effects on linearity can be softened by biasing the transistor at constant drain currents. These experimental observations can be explained by the change of threshold voltage, transconductance, subthreshold swing, and mobility degradation coefficient under HC stress.
Improvement in light-output efficiency of AlGaInP LEDs fabricated on stripe patterned epitaxy
(2005-12-01)
Lee, YJ
;
Tseng, HC
;
Kuo, HC
;
Wang, SC
;
Chang, CW
Quaternary AlGaInP light-emitting diodes (LEDs) operating at a wavelength of 630 nm with a stripe-patterned omni-directional reflector (ODR) were fabricated. It is demonstrated that the geometrical shape of stripe-patterned structure improves the light extraction efficiency by increasing the extraction of guided light. The optical and electrical characteristics of stripe-patterned ODR LEDs are presented and compared to typical ODR and distributed Bragg reflector (DBR) LEDs with the same epitaxial structure and emitting wavelength. It is shown that the output power of the stripe-patterned ODR LED exceeds that of the typical ODR and DBR LEDs by a factor of 1.15 and 2 times, respectively, and with an acceptable forward voltage of about 2.2 V.
Linearity and power characteristics of SiGeHBTs at high temperatures for RF applications
(2005-07-01)
Chen, KM
;
Peng, AS
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Huang, GW
;
Chen, HY
;
Huang, SY
In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.
Low temperature epitaxy of Si and Si1-xGex by utrahigh vacuum-chemical molecular epitaxy
(1997-01-01)
Huang, GW
;
Chen, LP
;
Chou, CT
;
Chen, KM
;
Tseng, HC
Pure Si2H6 and GeH4 are used to grow Si and Si1-xGex epilayers at 550 degrees C by ultrahigh vacuum-chemical molecular epitaxy. 0.1% B2H6 and 100 ppm PH3 diluted in H-2 are used as the p- and n-type dopant gases in Si/Si1-xGex epitaxy. The Ge mole fraction x and the growth rate of Si1-xGex epilayers show very strong dependence on the total source, gas flow rate ([GeH4]+[Si2H6]) and the source gas ratio ([GeH4]/[GeH4]+[Si2H6]). The results can be explained by the relationships of the source fluxes, relative incorporation efficiency at activated surface sites, and hydrogen desorption under different growth conditions. The boron concentration of Si1-xGex increases with increasing GeH4 flow rate by keeping Si2H6 and B2H6 how rates constant. It may be due to the increase of the surface sites which is caused by the increase of the hydrogen desorption rate when a higher Ge mole fraction epilayer is grown. The phosphorus concentrations of Si and Si1-xGex show different behavior with PH3 flux at higher PH3 flow rates while one increases Linearly and the other becomes saturated, respectively. These results can be explained by a model based on the different levels of the effects of phosphorus blocking of surface-activated sites between Si and Si1-xGex epilayers. This effect can also be used to explain the fact that a smaller decrease in the growth rates of Si1-xGex epilayers occurs at a higher PH3 flow rate. (C) 1997 American Institute of Physics.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
RF MOSFET characterization by four-port measurement
(2005-05-01)
Wu, SD
;
Huang, GW
;
Chen, KM
;
Tseng, HC
;
Hsu, TL
RF MOSFET's are usually measured in common source configuration by a 2-port network analyzer, and the common gate and commen drain S-parameters cannot be directly measured from a conventional 2-port test structure. In this work, a 4-port test structure for on-wafer measurement of RF MOSFET's is proposed. Four-port measurements for RF MOSFET's in different dimensions and the de-embedded procedures are performed up to 20 GHz. The S-parameters of the RF MOSFET in common source (CS), common gate (CG), and common drain (CD) configurations are obtained from a single DUT and one measurement procedure. The dependence of common source S-parameters of the device on substrate bias are also shown.
Study of nickel silicide contact on Si/Si1-xGex
(2003-09-01)
Yang, TH
;
Luo, GL
;
Chang, EY
;
Yang, TY
;
Tseng, HC
The properties of nickel silicide formed by depositing nickel on Si/P+ - Si1-xGex layer are compared with that of nickel germanosilicide on P+ - Si1-xGex layer formed by depositing Ni directly on P+ - Si1-xGex layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/P+ S Si1-xGex layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on P+ - Si1-xGex layer. In addition, small junction leakage current is also observed for nickel silicide on Si/P+ - Si1-xGex/N - Si diode. In summary, witha Si consuming layer on top of the Si1-xGex, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on Si1-xGex layer.
The role of a resist during O-2 plasma ashing and its impact on the reliability evaluation of ultrathin gate oxides
(1997-07-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Hsien, SK
Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm, becomes significant as the oxide thickness is scaled down below 6 nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.