Browsing by Author "Tseng, Kai-Hsin"

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A High-Troughput Radix-4 Log-MAP Decoder With Low Complexity LLR Architecture
(2009)
Chuang, Hsiang-Tsung
;
Tseng, Kai-Hsin
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm(2) on UMC 0.13 mu m standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.
An Area-Efficient Parallel Turbo Decoder Based on Contention Free Algorithm
(2009)
Tseng, Kai-Hsin
;
Chuang, Hsiang-Tsung
;
Tseng, Shao-Yen
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-mu m CMOS process.