Browsing by Author "Tseng, Shao-Yen"

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A Hardware-Efficient VLSI Implementation of a 4-Channel ICA Processor for Biomedical Signal Measurement
(2011)
Chen, Chiu-Kuo
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Chua, Ericson
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Fu, Chih-Chung
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Tseng, Shao-Yen
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Fang, Wai-Chi
This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.
A Highly-Integrated Biomedical Multiprocessor System for Portable Brain-Heart Monitoring
(2011)
Chua, Ericson
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Fang, Wai-Chi
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Chen, Chiu-Kuo
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Fu, Chih Chung
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Tseng, Shao-Yen
In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and a heart rate variability (HRV) analysis processor for monitoring heart electrocardiogram (ECG) signals. The multiprocessor chip implemented in 65nm CMOS technology comprises 368k gates and occupies a core area of 462k mu m(2). Simulated power consumption using a full operation test case reports 3.6mW under the condition of 1.0V core supply voltage and 24MHz clock operating frequency.
A Time-Frequency HRV Processor Using Windowed Lomb Periodogram
(2010)
Tseng, Shao-Yen
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Fang, Wai-Chi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a system for time-frequency analysis of heart rate variability (HRV) using windowed Lomb periodogram is proposed. The system is designed with considerations in SOC implementation for portable applications. Time-frequency analysis of HRV is achieved through a de-normalized Lomb periodogram with a sliding window configuration. The Lomb time-frequency distribution (TFD) is suited for power spectral density (PSD) analysis of unevenly spaced data and has been applied to the analysis of heart rate variability. The system has been implemented in hardware as an HRV processor and verified on FPGA. Artificial heart rate was used to evaluate the system as well as data from the MIT-BIH arrhythmia database and real EKG data. Simulations show that the proposed Lomb TFD is able to achieve better frequency resolution than short-time Fourier transform of the same hardware size.
A Wireless Biomedical Sensor Network using IEEE802.15.4
(2009)
Tseng, Shao-Yen
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Tsai, Chung-Han
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Lai, Yu-Sheng
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Fang, Wai-Chi
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電子工程學系及電子研究所
The advancements of wireless body area networks (WBAN) and wireless personal area networks (WPAN) has led to a recent increase of viable applications in wireless medical and healthcare devices. Developing biomedical sensors such as electroencephalograph (EEG) and electrocardiogram (ECG) sensors often require numerous connecting wires which may introduce noise and increase patient discomfort In this paper we propose a system design and realization of a wireless EEG and ECG sensor network focusing on issues such as time synchronization, bandwidth, and power constraints constituent of WBANs. Our WSN comprises three transmitting nodes for a total of four EEG channels and an ECG channel. We solve problems such as data throughput requirements for EEG and ECG signal processing as well as time synchronization of received data at the base station. This paper keeps in consideration the possible implementation of our proposed system onto a system-on-chip (SOC) by putting focus on the chip size and low power consumption of the analog-front-end system.
An Area-Efficient Parallel Turbo Decoder Based on Contention Free Algorithm
(2009)
Tseng, Kai-Hsin
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Chuang, Hsiang-Tsung
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Tseng, Shao-Yen
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Fang, Wai-Chi
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電子工程學系及電子研究所
In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-mu m CMOS process.
An Effective Heart Rate Variability Processor Design Based on Time-Frequency Analysis Algorithm Using Windowed Lomb Periodogram
(2010-01-01)
Tseng, Shao-Yen
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Fang, Wai-Chi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a system for time-frequency analysis of heart rate variability (HRV) using a fast windowed Lomb periodogram is proposed. Time-frequency analysis of HRV is achieved through a de-normalized fast Lomb periodogram with a sliding window configuration. The Lomb time-frequency distribution (TFD) is suited for spectral analysis of unevenly spaced data and has been applied to the analysis of HRV. The system has been implemented in hardware as an HRV processor and verified on FPGA. Simulations show that the proposed Lomb TFD is able to achieve better frequency resolution than short-time Fourier transform of the same hardware size. The proposed system is suitable for portable monitoring devices and as a biomedical signal processor on an system-on-chip (SOC) design.
An EKG System-on-Chip for Portable Time-Frequency HRV Analysis
(2011)
Tseng, Shao-Yen
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Fang, Wai-Chi
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an EKG system-on-chip (SOC) for portable health care and home monitoring applications. The EKG system acquires three channel EKG from front-end circuits and includes functions such as beat detection, interval calculation, and time-frequency analysis of heart rate variability (HRV) in real-time. An HRV analysis engine has also been developed using Lomb periodogram for time-frequency power spectral density (PSD) analysis of heart rate. HRV analysis as well as raw data can be transmitted via Bluetooth to a cell phone or remote station through a UART interface.
Design of heart rate variability processor for portable 3-lead ECG monitoring system-on-chip
(2013-04-01)
Fang, Wai-Chi
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Huang, Hsiang-Cheh
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Tseng, Shao-Yen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The worldwide population of people over the age of 65 has been predicted to more than double from 1990 to 2025. Therefore, ubiquitous health-care systems have become an important topic of research in recent years. In this paper, an integrated system for portable electrocardiography (ECG) monitoring, with an on-board processor for time-frequency analysis of heart rate variability (HRV), is presented. The main function of proposed system comprises three parts, namely, an analog-to-digital converter (ADC) controller, an HRV processor, and a lossless compression engine. At the beginning, ECG data acquired from front-end circuits through the ADC controller is passed through the HRV processor for analysis. Next, the HRV processor performs real-time analysis of time-frequency HRV using the Lomb periodogram and a sliding window configuration. The Lomb periodogram is suited for spectral analysis of unevenly sampled data and has been applied to time-frequency analysis of HRV in the proposed system. Finally, the ECG data are compressed by 2.5 times using the lossless compression engine before output using universal asynchronous receiver/transmitter (UART). Bluetooth is employed to transmit analyzed HRV data and raw ECG data to a remote station for display or further analysis. The integrated ECG health-care system design proposed has been implemented using UMC 90 nm CMOS technology. (C) 2012 Elsevier Ltd. All rights reserved.
Portable Brain-Heart Monitoring System
(2010)
Fu, Chih-Chung
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Chen, Chiu-Kuo
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Tseng, Shao-Yen
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Kang, Shih
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Chua, Ericson
A portable brain-heart monitoring system is proposed to integrate and miniaturize those heavy equipments in the hospitals. The system comprises a 4-channel independent component analysis (ICA) engine for artifact removal from EEG, a heart-rate variability (HRV) analysis engine for on-line HRV analysis and a diffuse optical tomography (DOT) engine for reconstruction of the absorption coefficient image of the brain tissue. A lossless compression module achieves 2.5 compression ratio is also employed to reduce the power consumption of the wireless transmission. EEG, EKG and near-infrared signals acquired from the analog front-end IC are processed in real-time or bypassed according to user configurations. Processed data and raw data are compressed and sent to a remote science station by a commercial Bluetooth module for further analysis and 3-D visualization and remote diagnosis. The ICA and HRV engine are verified by real EEG and EKG signals while the DOT engine is verified by an experimental model. The system is implemented using UMC 65nm CMOS technology, and the core size is 680x680 um(2), and the estimated power consumption of the chip working at 24 MHz under full mode is 3.6 mW.