Browsing by Author "Tseng, TK"

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Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
(2004-01-15)
Ker, MD
;
Tseng, TK
;
電機學院
;
College of Electrical and Computer Engineering
A novel electrostatic discharge (ESD) protection device with a threshold voltage of similar to0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an active ESD device has the fastest turn-on speed and the lowest turn-on voltage to effectively protect the internal circuits with a much thinner gate oxide in future sub-0.1 mum CMOS technology. The proposed active ESD device is fully process-compatible to the general sub-quarter-micron CMOS process.
Evaluation on ESD robustness of UPS diode and TFT device by transmission line pulsing (TLP) technique
(2003)
Ker, MD
;
Tseng, TK
;
Yang, SC
;
Shih, A
;
Tsai, YM
ESD robustness of Low Temperature Poly-Si (LTPS) diodes and TFT devices has been investigated in this paper. By using the Transmission Line Pulsing (TLP) techniques, the It2 (secondary breakdown current) of LTPS diodes and TFT devices were measured. To evaluate the ESD robustness of components for ESD protection, the shifts of breakdown voltage and cut-in voltage of LTPS diode and TFT devices after TLP stress are considered into failure threshold judgment. From the experimental results, It2 of LTPS diodes under forward-biased stress is better than that of LTPS TFT devices. Furthermore, the It2 of LTPS TFT devices under reverse-biased stress is more robust than it under forward-biased stress. Such investigation results can help us to design a successful ESD protection for the circuits on glass.
Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology
(2003)
Ker, MD
;
Tseng, TK
;
電機學院
;
College of Electrical and Computer Engineering
A novel electrostatic discharge (ESD) protection concept by using the already-on device is proposed to effectively protect CMOS integrated circuits (IC) in nanoscale CMOS processes against ESD stress. Such an already-on NMOS device is designed to have a threshold voltage of similar to0V, or even negative. When the IC is under the ESD zapping conditions, such already-on NMOS in CMOS IC are initially standing in the turn-on state and ready to discharge ESD current during any ESD zapping. So, such already-on NMOS has the fastest turn-on speed and the lowest trigger-on voltage to effectively protect the internal circuits with a much thinner gate oxide (similar to15Angstrom) in future sub-100nm CMOS technology. To keep such already-on devices off when the IC is under normal circuit operating condition, an onchip negative voltage generator realized by the diodes and capacitors is used to bias the gates of such already-on devices. The proposed already-on device and the on-chip negative voltage generator are fully process-compatible to the general sub-100nm CMOS processes.