Browsing by Author "Tseng, Tien-Hung"

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Lifetime Reliability Trojan based on Exploring Malicious Aging
(2018-01-01)
Tseng, Tien-Hung
;
Li, Shou-Chun
;
Wu, Kai-Chiang
;
資訊工程學系
;
Department of Computer Science
Due to escalating complexity of hardware design and manufacturing, integrated circuits (ICs) are designed and fabricated in multiple nations, so are software tools. It makes hardware security become more subject to various kinds of tampering in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information or cause the failure of a system. Reliability Trojan is one of the main categories of HTH attacks because its behavior is progressive and thus hard to be detected, or not considered malicious. In this work, we propose to insert reliability Trojan into a circuit which can finely control the circuit lifetime as specified by attackers (or even designers), based on manipulating BTI-induced aging behavior in a statistical manner, with the consideration of process variations (PVs). Experimental results show that, given a specified lifetime target and under the influence of PVs, the circuit is highly likely to fail within a desired lifetime interval, at the cost of little area overhead.
MAUI: Making Aging Useful, Intentionally
(2018-01-01)
Wu, Kai-Chiang
;
Tseng, Tien-Hung
;
Li, Shou-Chun
;
資訊工程學系
;
Department of Computer Science
Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating these lime-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its overall performance degradation due to aging can be minimized, that is, the lifespan can be maximized. On average, 25% aging tolerance can be achieved with insignificant design overhead.
Workload-Aware Lifetime Trojan based on Statistical Aging Manipulation
(2017-01-01)
Tseng, Tien-Hung
;
Wang, Shu-Sheng
;
Chen, Jian-You
;
Wu, Kai-Chiang
;
資訊工程學系
Due to escalating complexity of hardware design and manufacturing, not only are integrated circuits (ICs) designed and fabricated in multiple nations, but also software tools may be supplied worldwide. It makes hardware security become more subject to various kinds of tampering in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information or cause the failure of a system. Reliability Trojan is one of the main categories of HTH attacks because its behavior is progressive and is thus not trivial to be detected, or not considered malicious. In this work, we propose to insert reliability Trojan into a circuit which can finely controls the circuit lifetime as specified by attackers (or even designers), based on manipulating BTI-induced aging behavior in a statistical manner. Experimental results show that, given a specified lifetime target, the resulting lifetime can mostly be bounded within 90% similar to 110% of the target. Instead, in a typical design considering pessimistic corners, the resulting lifetime is usually far longer than the target.