Browsing by Author "Tseng, WT"

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A comparative study on the roles of velocity in the material removal rate during chemical mechanical polishing
(1999-05-01)
Tseng, WT
;
Chin, JH
;
Kang, LC
;
機械工程學系
;
Department of Mechanical Engineering
Relative velocities between the flowing slurry and selected points on a 150 mm wafer and nonuniformity of velocity are calculated given the known carrier speed, platen speed, and pad-to-wafer distance. Based on simulation results, the combination of a high pad rpm, a medium wafer rpm, and a large pad-to-wafer distance should give rise to a minimum nonuniformity of velocity. Chemical mechanical polish (CMP) removal rates data are fitted to the original Preston equation, Tseng's model,(1) and a modified Preston equation which incorporates the deterioration characteristics of abrasives into the removal rate model. Theoretical removal rate data predicted by Tseng's model and the modified Preston equation exhibit much better agreement with experimental removal rates than those by the original Preston equation. The nonlinear dependence of removal rate on velocity can be explained by the deterioration in slurry abrasion capability. (C) 1999 The Electrochemical Society. S0013-4651(97)11-028-X. All rights reserved.
A modified multi-chemical spray cleaning process for post shallow trench isolation chemical mechanical polishing cleaning application
(1998-11-02)
Wang, YL
;
Wang, TC
;
Wu, J
;
Tseng, WT
;
Lin, CF
Chemical mechanical planarization (CMP) has become widely accepted for the formation of device interconnect structures. Shallow trench isolation technology (STI) utilizes CMP and has been applied to deep-sub-micron processes. Poly Si, CVD Si or SiO2 can be grown or deposited in the trench and planarized by a CMP process. However, the typical wafer surface is contaminated with slurry particles and metallic impurities after the CMP process. The silica particles may damage the VLSI patterns and the metallic impurities can induce many crystal defects in Si wafers during the following furnace processing. Therefore, the post CMP clean is a very important step for the STI process. However, the wafer for poly-Si surface is hydrophobic, SiO2 surface is hydrophilic and Si film is very easy to charge up. Thus, the defect can be difficult to remove by a conventional cleaning technique. In this study: we propose the use of a modified multi-chemicals spray cleaning process for post STI CMP cleaning. We used a modified and heated ammonia/peroxide mix (APM) clean with an ammonia pre-soak and an HF step to etch a thin layer for the removal of trapped metallic ions which can be followed by a hydrochloric/peroxide mix (HPM) clean process to assist in the removal of metallic ions. (C) 1998 Elsevier Science S.A. All rights reserved.
A modified multi-chemicals spray cleaning process for post-CMP cleaning application
(1998-01-01)
Wang, YL
;
Liu, C
;
Feng, MS
;
Tseng, WT
;
材料科學與工程學系
Chemical mechanical planarization (CMP) has become widely accepted for the planarization of device interconnect structures in deep submicron semiconductor manufacturing. Attractive features of CMP include (i) global planarization and (ii) low defect and contamination level. The main challenge of cleaning is to remove the residual particles as well as the metallic contamination. In this paper, a modified post-CMP clean up-multi-chemicals spray cleaning process-is addressed in detail. This new process has been successfully applied to both oxide and tungsten CMP cleaning. The process provides comparable defect performance and excellent removal of metallic contamination to the scrubbing process which has been widely accepted in current post-CMP cleaning usage. The new clean up development strategy also contributes to their low cost of ownership (Co0) and good process flexibility as well as the minimizing cross-contamination. (C) 1998 Elsevier Science S.A.
A modified multi-chemicals spray cleaning process for post-CMP cleaning application
(1998-01-01)
Wang, YL
;
Liu, C
;
Feng, MS
;
Tseng, WT
;
材料科學與工程學系
Chemical mechanical planarization (CMP) has become widely accepted for the planarization of device interconnect structures in deep submicron semiconductor manufacturing. Attractive features of CMP include (i) global planarization and (ii) low defect and contamination level. The main challenge of cleaning is to remove the residual particles as well as the metallic contamination. In this paper, a modified post-CMP clean up-multi-chemicals spray cleaning process-is addressed in detail. This new process has been successfully applied to both oxide and tungsten CMP cleaning. The process provides comparable defect performance and excellent removal of metallic contamination to the scrubbing process which has been widely accepted in current post-CMP cleaning usage. The new clean up development strategy also contributes to their low cost of ownership (Co0) and good process flexibility as well as the minimizing cross-contamination. (C) 1998 Elsevier Science S.A.
A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarization
(1999-06-22)
Lin, CF
;
Tseng, WT
;
Feng, MS
;
Wang, YL
;
材料科學與工程學系
A multilayer thin film structure (SiO2/SiNx/SiO2) with a one-step chemical-mechanical polish (CMP) process is developed for shallow trench filling and planarization for ULSI devices in the quarter micron regime. By fine-tuning the plasma-enhanced chemical vapor deposition (PECVD) conditions we successfully modified the stoichiometry and other characteristics of the as-deposited SiNx and oxide films. As these film characteristics are changed, the CMP removal rate selectivity between sacrificial oxide and nitride stopper layer can also be adjusted. Correspondingly, the CMP process latitude for shallow trench isolation in 0.25 mu m memory devices can be broadened by sequentially depositing multilayered oxide and nitride films with adjustable characteristics and CMP removal rates. Dishing-free wide trench areas with excellent planarity can be achieved through the integration of the proposed multilayered PECVD oxide/nitride scheme and the one-step CMP process. (C) 1999 Elsevier Science S.A. All rights reserved.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical-mechanical polishing and material characteristics of plasma-enhanced chemically vapor deposited fluorinated oxide thin films
(1997-03-01)
Tseng, WT
;
Hsieh, YT
;
Lin, CF
;
Tsai, MS
;
Feng, MS
The chemical-mechanical polishing (CMP) process has been proven to be the most promising method for accomplishing global planarization. In this paper, results of chemical-mechanical polishing of fluorinated silicon dioxide (SiOF) thin films are presented. Nanohardness, elastic modulus, and bonding structure of fluorinated silicon dioxides are characterized in order to evaluate their correlations with CMP performance. The results show that under fixed chemistry and mechanical parameters, the CMP removal rate increases significantly with increasing fluorine content in the oxides due to the lower hardness and elastic modulus in the films. Higher CMP removal rate is observed for fluorinated oxides polished with slurry of pH 10 relative to pH 9. Compared with undoped oxides, SiOF films are more sentisitive to chemical and moisture attacks as reflected by the post-CMP increase in refractive index.
Chemical-mechanical polishing of low-dielectric-constant spin-on-glasses: film chemistries, slurry formulation and polish selectivity
(1997-10-31)
Wang, YL
;
Liu, C
;
Chang, ST
;
Tsai, MS
;
Feng, MS
Alkyl siloxane-based low-dielectric-constant (low-k) spin-on-glass (SOG) thin films with varying amounts of organic content were subjected to polishing experiments using silica-and ZrO2-based slurries with a variety of additives, As the amount of organic content in SOG increases, the chemical-mechanical polishing (CMP) removal rate decreases with silica-based potassium hydroxide-added slurry. On the other hand, zirconia-based slurry resulted in higher removal rates for both SOG (>400 nm/min) and thermal oxide and an adjustment in polish selectivity (related to thermal oxide) ranging from 1.2 to 9.1 can be achieved by adding various amounts of tetra-alkyl substituted ammonium hydroxide. Post-CMP materials characterization by Fourier transform infrared spectroscopy (FTIR) and atomic force microscopy (AFM) shows the chemical stability and CMP compatibility of SOG thin films. (C) 1997 Elsevier Science S.A.
CMP of fluorinated silicon dioxide: Is it necessary and feasible?
(1997-02-01)
Tseng, WT
;
Hsieh, YT
;
Lin, CF
;
交大名義發表
;
National Chiao Tung University
Use of low-permittivity (low-k) fluorinated silicon dioxides (F-SiO2) for inter-metal dielectric (IMD) applications makes it necessary to evaluate the compatibility of chemical-mechanical polishing (CMP) in device fabrication. Basic material characteristics (such as adhesion, gap fill, step coverage, stress, hardness, chemical stability, moisture permeation, and wet etching rate) should be investigated thoroughly to assess CMP performance. With increasing fluorine content in the oxides, the low-k dielectric exhibits increased chemical reactivity and water absorption. These properties enhance the CMP removal rate, but degrade post-CMP material reliability and electrical performance. This article examines the CMP performance of F-SiO2 used to provide a low dielectric constant in IMD applications.
Effects of corrosion environments on the surface finishing of copper chemical mechanical polishing
(1997-10-31)
Wang, MT
;
Tsai, MS
;
Liu, C
;
Tseng, WT
;
Chang, TC
Copper chemical mechanical polishing (Cu-CMP) was investigated using slurries containing alumina abrasive and various types and concentrations of oxidizer, as well as benezotriazole (BTA) additive. We found that the corrosion rate of copper film decreases with increasing BTA concentration in 3 vol.% HNO3 solution, but the passivation effect of BTA saturates as the concentration reaches about 0.01 M. On the other hand, a small amount of H2O2 in H2O2/XJFW8099 slurry enhances the corrosion rate dramatically, while abundance of H2O2 in the slurry suppresses the corrosion reaction effectively. The polishing rate and its non-uniformity decrease with increasing volume ratio of H2O2 in H2O2/XJEW8099 slurry. A very smooth surface with a removal rate of 363.0 nm/min was obtained using the slurry of 1/1 ratio. Depletion of H2O2 in the slurry can result in more abrasive residuals as well as a rougher surface; the surface roughness increases from 0.3 to 9.9 nm as the H2O2/XJFW8099 ratio decreases from 1/1 to 1/4. Our results indicate that the corrosion rate, polishing rate and surface roughness of copper films are sensitively dependent on the type and concentration of oxidizer as well as the BTA additive. (C) 1997 Elsevier Science S.A.
Effects of film stress on the chemical mechanical polishing process
(1999-11-01)
Tseng, WT
;
Wang, YH
;
Chin, JH
;
機械工程學系
;
Department of Mechanical Engineering
A theoretical model is constructed to simulate the pressure distribution arising from wafer curvature (film stress) during chemical mechanical polishing (CMP), based on theories of elastic contact stress. Results from oxide CMP experiments suggest that the wafer curvature results in a nonuniform polish rate distribution across the wafer, in agreement with the simulation based on the model. This stress-dependent polish nonuniformity is attributed to the nonuniform pressure distribution across the wafer, induced by the wafer radius of curvature (film stress). Also, it was found that the magnitude of bride film stress itself has little effect on removal rate. Oxides with tensile stress tend to have a weakened bond structure and enhanced chemical reactivity, both of which result in slightly higher removal rates. The reverse is true for oxides with compressive stress. Deviations from the model prediction mag. result from the stress induced by slurry flow, local variations in wafer shape and form, and pad surface properties. (C) 1999 The Electrochemical Society. S0013-4651(99)03-063-3. All rights reserved.
Effects of mechanical characteristics on the chemical-mechanical polishing of dielectric thin films
(1996-12-15)
Tseng, WT
;
Liu, CW
;
Dai, BT
;
Yeh, CF
;
電子工程學系及電子研究所
The effects of as-deposited (intrinsic) stress, externally applied (extrinsic) stresses, hardness, and modulus of various dielectric firms on chemical-mechanical polishing (CMP) removal and post-CMP cleaning processes are studied in this article. Intrinsic stresses of the polished dielectrics do not contribute directly to the CMP removal rate. Extrinsic stresses including normal and shear components are calculated using principles of elasticity and fluid mechanics respectively and their roles in the material removal process are discussed. Theoretical evaluation and experimental results both suggest that hardness and modulus are the two most important material characteristics affecting the CMP process. Efficiency of post-CMP particle extraction can be monitored using an adhesion probability which is related to the hardness of wafer and pad. Tn addition, particle removal rate can be remarkably enhanced by increasing pressure (normal stress) while increasing pad rotation speed (shear stress) contributes little to reduce the particle count.
Integration of modified plasma-enhanced chemical vapor deposited tetraethoxysilane intermetal dielectric and chemical-mechanical polishing processes for 0.35 mu m IC device reliability improvement
(1997-09-01)
Wang, YL
;
Tseng, WT
;
Feng, MS
;
材料科學與工程學系
;
電子工程學系及電子研究所
The process of interlevel dielectrics (ILD) between poly-Si and metal is critical to device characteristics and reliability. Also, the shrinking design rules demand greater hot carrier reliability, which is strongly influenced by the ILD process. In this paper we describe a process for improving the reliability of 0.35 mu m devices by using modified plasma-enhanced chemical vapor deposited tetraethoxysilane (PECVD-TEOS) N2O-rich or O-2-rich ILD films which contain less hydrogen concentration and excellent moisture resistance, and less mobile ion penetration after chemical-mechanical polishing (CMP), relative to standard PE-TEOS oxides. The hot carrier lifetime and the held isolation device threshold voltage are monitored and compared between devices with ILD layers based on different combinations of subatomespheric O-3-TEOS borophosphorus silicate glass (BPSG), standard PE-TEOS, O-2-rich and N2O-rich oxides. The material characteristics contributing to the reduction in post-CMP mobile ion levels and the improvement in device reliability will be discussed.
Integration of modified plasma-enhanced chemical vapor deposited tetraethoxysilane intermetal dielectric and chemical-mechanical polishing processes for 0.35 mu m IC device reliability improvement
(1997-09-01)
Wang, YL
;
Tseng, WT
;
Feng, MS
;
材料科學與工程學系
;
電子工程學系及電子研究所
The process of interlevel dielectrics (ILD) between poly-Si and metal is critical to device characteristics and reliability. Also, the shrinking design rules demand greater hot carrier reliability, which is strongly influenced by the ILD process. In this paper we describe a process for improving the reliability of 0.35 mu m devices by using modified plasma-enhanced chemical vapor deposited tetraethoxysilane (PECVD-TEOS) N2O-rich or O-2-rich ILD films which contain less hydrogen concentration and excellent moisture resistance, and less mobile ion penetration after chemical-mechanical polishing (CMP), relative to standard PE-TEOS oxides. The hot carrier lifetime and the held isolation device threshold voltage are monitored and compared between devices with ILD layers based on different combinations of subatomespheric O-3-TEOS borophosphorus silicate glass (BPSG), standard PE-TEOS, O-2-rich and N2O-rich oxides. The material characteristics contributing to the reduction in post-CMP mobile ion levels and the improvement in device reliability will be discussed.
Modeling of the wear mechanism during chemical-mechanical polishing
(1996-02-01)
Liu, CW
;
Dai, BT
;
Tseng, WT
;
Yeh, CF
;
電子工程學系及電子研究所
A model based on statistical method and elastic theory is presented to describe the wear mechanism of the silicon wafer surface during chemical-mechanical polishing. This model concerns the effects of applied pressure and relative velocity between the pad and the wafer on the removal rate during polishing and is capable of delineating the role of the mechanical properties of the slurry particles and the films to be polished. The removal rate is dependent on the elastic moduli of slurry particle and polished film. Comparisons with experimental data demonstrate the validity of the model for predicting relative removal rate for various dielectric films.
Modified double-layer PECVD passivation films for improving nonvolatile memory IC performance
(1997)
Lin, CF
;
Tseng, WT
;
Feng, MS
;
Chang, YF
;
交大名義發表
Characteristics of PECVD SiO2SiNx passivation layers are modified to improve and optimize electrical performances such as read-write (R/W) cycle and hot carrier reliability of floating-gate nonvolatile memory devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (R.L) and wet etch rates. These modifications in film characteristics also correspond to longer R/W cycles and lower % hot-carrier linear drain current (I-dlin) degradation. An increase in R.I, from 1.520 to 1.675 translates to a rise in R/W cycles from 17.3K to 32K and a fall in I-dlin from 8.2 % to 4.9 %. Further improvement in device performance is fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing SiH4/NH3 gas flow rate ratio during the PECVD nitride deposition process. The nitride films deposited herein contain lower hydrogen content and exhibit lower BOE etch rates and compressive stress. Water diffusion from oxide and hydrogen release from nitride are both responsible for hot carrier drain current degradation and loss in read-write cycles. The utilization of high-RI oxide in conjunction with a low hydrogen content nitride would yield the optimal device reliability.
Modified polycrystalline silicon chemical-vapor deposition process for improving roughness at oxide/polycrystalline silicon interface
(2005-01-24)
Chang, JJ
;
Hsieh, TE
;
Wang, YL
;
Tseng, WT
;
Liu, CP
A new modified low pressure chemical-vapor deposition process for stacked polysilicon (poly-Si) films is developed in this study. The proposed stacked film process combines polysilicon with amorphous silicon films. In this process, polysilicon film was deposited first at 630degreesC, followed by a continuous temperature decrease down to 560degreesC for the deposition of amorphous silicon film. It was found that the doped stacked polysilicon films deposited by this process result in lowering of surface roughness, together with reduction of the (311) phase of the doped amorphous silicon and (110) phase of the doped polysilicon. As a consequence, device performance based on the stacked films also improves. Results of surface roughness analysis indicated that the doped stacked polysilicon film has a root-mean square surface roughness (Rrms) of 78 A, which is smaller than those of doped conventional (630degreesC) polysilicon film (Rrms=97 A), and doped amorphous silicon film (Rrms=123 A, deposited at 560degreesC). Transmission electron microscopic (TEM) observation performed at oxide/polysilicon interface showed that the conventional (630degreesC) oxide/polysilicon interface has high angle grain boundaries on the polysilicon side, which may induce leakage current around the interfacial area. (C) 2004 Elsevier B.V. All rights reserved.