Browsing by Author "Tseng, Wei-Hsin"

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A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz
(2011-12-01)
Tseng, Wei-Hsin
;
Fan, Chi-Wei
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 x 750 mu m(2). It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
(2011-01-01)
Tseng, Wei-Hsin
;
Wu, Jieh-Tsorng
;
Chu, Yung-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.