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Browsing by Author "Tseng, Wenliang"

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    Passive reduced-order macro-modeling for linear time-delay interconnect systems
    (2006-11-01)
    Tseng, Wenliang
    ;
    Liu, Chien-Nan Jimmy
    ;
    Su, Chauchin
    ;
    電控工程研究所
    ;
    Institute of Electrical and Control Engineering
    This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.