Browsing by Author "Tseng, YK"

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A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
(1998-10-01)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS; buffer circuit structure is used to achieve high-speed operation under low supply voltage, Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed (DCB)-B-2-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs, HSPICE simulation results have shown that the new (DCB)-B-2-BiCMOS at 1.5 V and the new DC2-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input (DCB)-B-2-BiCMOS XOR/XNOR gate chain fabricated by 0.8-mu m BiCMOS technology that the speed of (DCB)-B-2-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed (DCB)-B-2-BiCMOS and DC2-BiCMOS logic circuits are feasible for low-voltage, high-speed applications.
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
(1998-10-01)
Tseng, YK
;
Wu, CY
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS; buffer circuit structure is used to achieve high-speed operation under low supply voltage, Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed (DCB)-B-2-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs, HSPICE simulation results have shown that the new (DCB)-B-2-BiCMOS at 1.5 V and the new DC2-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input (DCB)-B-2-BiCMOS XOR/XNOR gate chain fabricated by 0.8-mu m BiCMOS technology that the speed of (DCB)-B-2-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed (DCB)-B-2-BiCMOS and DC2-BiCMOS logic circuits are feasible for low-voltage, high-speed applications.
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
(1997)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New full-swing BiCMOS differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. HSPICE simulations results show that as compared to Bootstrapped BiCMOS CPL logic gate, the new DC2(B)-BiCMOS three-input XOR/XNOR gate with 1.5V supply voltage and 0.5pF output XOR/XNOR gate with 1.5V supply voltage and 0.5pF output loading has about 80% and 86% improvement in the propagation delay and power-delay product, respectively, in 0.8 mu m technology. Moreover, the DC2-BiCMOS with 0.5pF output loading at 2V offers about 57% improvement in the propagation delay time over Pass Transistor BiCMOS (PT-BiCMOS) differential logic gate.
A new true-single-phase-clocking (TSPC) BiCMOS dynamic pipelined logic
(1998)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New true-single-phase-clocking BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. The circuit performance of the new BiCMOS dynamic logic circuits and BiCMOS dynamic latch logic circuits are simulated by using HSPICE in 1 mu m BiCMOS technology. Simulation results have shown that the operating frequency of the pipelined system which is constructed by the new dynamic latch logic circuits, is 204.1 MHz under 1.5 pF output loading at 2.3 V. It is 2.86 times of the operating frequency in the CMOS TSPC dynamic pipelined system.
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications
(1999-01-01)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed, In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1-mu m BiCMOS technology, Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked RIGS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively, Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1-mu m BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, Low-voltage dynamic pipelined system applications.
Bipolar bootstrapped multi-emitter BiCMOS ((BM)-M-2-BiCMOS) logic for low-voltage applications
(1996)
Wu, CY
;
Tseng, YK
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new full-swing BiCMOS logic circuits called the bootstrapped multi-emitter BICMOS ((BM)-M-2-BiCMOS) logic is proposed and analyzed. HSPICE logic is simulations have been performed to compare speed performance of the new BICMOS logic circuit with those of CMOS, conventional BICMOS, and Bootstrapped BICMOS (BS-BICMOS) logic circuits, in 1 mu m technology. It has been shown that as compared to BS-BICMOS (CMOS) logic gate, the new (BM)-M-2-BiCMOS 3-input NAND gate with 2V supply voltage and 0.5pF output loading has about 36% (72%) improvement in the propagation delay time whereas the (BM)-M-2-BiCMOS 5- and 7- input NAND gates have 1.84 (2.4) and 2.16 (3.1) times of improvement, respectively. This advantageous performance makes the (BM)-M-2-BiCMOS feasible in many low-voltage BICMOS applications.
Raman scattering and efficient UV photoluminescence from well-aligned ZnO nanowires epitaxially grown on GaN buffer layer
(2005-05-12)
Cheng, HM
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Hsu, HC
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Tseng, YK
;
Lin, LJ
;
Hsieh, WF
Optical phonon confinement and efficient UV emission of ZnO nanowires were investigated in use of resonant Raman scattering (RRS) and photoluminescence (PL). The high-quality ZnO nanowires with diameters of 80-100 nm and lengths of several micrometers were epitaxially grown through a simple low-pressure vapor-phase deposition method at temperature 550 &DEG; C on the precoated GaN(0001) buffer layer. The increasing intensity ratio of n-order longitudinal optical (LO) phonon (A(1) (nLO)/E-1 (nLO)) with increasing scattering order in RRS reveals the phonon quantum confinement as shrinking the diameter of ZnO nanowires. The exciton-related recombination near the band-edge transition dominate the UV emissions at room temperature as well as at low temperature that exhibits almost no other nonstoichiometric defects in the ZnO nanowires.
Selective growth of ZnO nanorods on pre-coated ZnO buffer layer
(2004-02-01)
Hsu, HC
;
Tseng, YK
;
Cheng, HM
;
Kuo, JH
;
Hsieh, WF
Hexagonal ZnO nanorods have been selectively synthesized via vapor-solid process without gold catalysis on. a precoated ZnO buffer layer. The presence of nanometer-sized pits or hills on the surface of ZnO buffer layer provides nucleation sites to which the zinc vapor is transferred and condensed. Followed by immediate oxidation the ZnO nanorods were grown on the. buffer layer. Contrarily, the SEM images hardly show growth of irregular ZnO nanometer-sized products on the bare sapphire substrate. Besides a strong ultra-violet emission at 3.26 eV observed at room temperature, the coupling strength of the radiative transition to LO-phonon polarization field was deduced in use of the Huang-Rhys factor. from low temperature photoluminescence spectra to show that single crystalline ZnO nanorods. (C) 2003 Elsevier B.V. All rights reserved.
Two-step oxygen injection process for growing ZnO nanorods
(2003-12-01)
Tseng, YK
;
Hsu, HC
;
Hsieh, WF
;
Liu, KS
;
Chen, IC
Uniform hexagonal prismatic zinc oxide rods were grown over the entire alumina substrate at 550 degreesC using a two-step oxygen injection process, whether the substrates were coated with a catalyst or not. X-ray diffraction showed that all of the depositions exhibited a preferred orientation in the (002) plane. The influence of oxygen concentration was investigated by changing the oxygen flow rate. Oxygen concentration affected the size of ZnO nanorods, especially the diameter. The ZnO nanorods were further checked using high-resolution transmission electron microscopy, photoluminescence, Raman spectroscopy, and room-temperature ultraviolet lasing. The results showed that the rods were single crystals and had excellent optical properties. By observing the growth process, we found that the diameter increased slowly, but the longitudinal growth rate was very high. The growth of ZnO nanorods revealed that the uniform hexagonal prismatic ZnO nanorods were synthesized through vapor deposition growth and a self-catalyzed vapor-liquid-solid (VLS) process.