Browsing by Author "Tsou, Y. -C."

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Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
(2017-01-01)
Su, C. -J.
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Hong, T. -C.
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Tsou, Y. -C.
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Hou, F. -J.
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Sung, P. -J.
Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. I-ON/I-OFF ratios higher than 10(7) and 10(6) for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
(2016-01-01)
Lee, Y. -J.
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Hong, T. -C.
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Hsueh, F. -K.
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Sung, P. J.
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Chen, C. -Y.
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high I-ON/I-OFF ratio and low subthreshold swing (S.S. similar to 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.