Browsing by Author "Tsui, BY"

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0.1 mu m poly-Si thin film transistors for system-on-panel (SoP) applications
(2005)
Tsui, BY
;
Lin, CP
;
Huang, CF
;
Xiao, YH
;
電子工程學系及電子研究所
Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mu m channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.
A comprehensive study on the FIBL of nanoscale MOSFETs
(2004-10-01)
Tsui, BY
;
Chin, LF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I-off with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 run. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.
A novel 25-nm modified Schottky-barrier FinFET with high performance
(2004-06-01)
Tsui, BY
;
Lin, CP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance modified Schottky barrier (MSB) FinFET with 25-nm channel length and fully silicided source/drain (S/D) is proposed for the first time. Using an implant-to-silicide technique, an ultrashort and defect-free S/D extension can be formed at temperature as low as 600 degreesC. The MSB FinFET exhibits better current-voltage characteristics than those of published Schottky barrier devices and FinFETs. With 4-nm-thick gate oxide, the I-on /I-off current ratio higher than 10(9) is achieved. The subthreshold swing of 25-nm and 49-nm MSB FinFETs is 83 and 64.5 mV/dec at room temperature. The advantage of low thermal budget relaxes the thermal stability issue for metal gate/high-kappa dielectric integration. It is believed that the proposed MSB FinFET would be a very promising nano device.
A novel fully self-aligned process for high cell density trench gate power MOSFETs
(2004)
Tsui, BY
;
Gan, TC
;
Wu, MD
;
Chou, HH
;
Wu, ZL
A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 mOmega-cm(2) with 1.5um cell pitch and 35V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization the thickness of n- drift layer and n+ substrate, specific on-resistance lower than 0.1 mOmega-cm(2) with 0.6um technology could be expected.
A novel wafer reclaim method for amorphous SiC and carbon doped oxide films
(2005-11-01)
Tsui, BY
;
Fang, KL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Amorphous SiC (a-SiC) films are the most promising dielectric diffusion barriers to replace silicon nitride in Cu-interconnect technology. However, reclaim of wafers with a-SiC films is a challenge issue for mass production. In this paper, a novel wafer reclaim method is proposed. It is observed that a-SiC can be oxidized to SiO2 in both dry O-2 and steam ambients at temperatures as low as 550 degrees C. The oxidation mechanism can be described by the Deal-Grove model that is traditionally used to describe oxidation of Si. Experiments prove that the oxidation process is clean and uniform. It is also observed that carbon doped oxide (CDO) films can be oxidized easily, too. Therefore, oxidation followed by HF etching could be a universal process to reclaim wafers deposited with a-SiC or CDO films. Since the oxidation rate of Si substrates at medium temperatures is much lower than that of a-SiC and CDO films, the oxidation process is virtually self-limiting. Compared with a traditional reclaim method based on wafer polishing, this universal oxidation-etching method exhibits great benefits in terms of low cost, high throughput, and the ability to perform nearly unlimited numbers of reclaim cycles.
A novel wafer reclaim method for silicon carbide film
(2003)
Tsui, BY
;
Fang, KL
;
Wu, CH
;
Li, YH
;
電子工程學系及電子研究所
As feature size keeps shrinking down, it is expected that amorphous SiC will replace Si3N4 in the Cu dual-damascene structure soon. SiC is chemically inert and is hard to be etched by wet processing. This property become adverse effect from the wafer reclaiming point of view. In this work, a novel wafer reclaiming method of oxidation followed by HF etching is proposed. Comparing with traditional reclaim method of wafer polish, this novel method exhibits great benefits of low cost, high throughput, and almost unlimited reclaim times.
Anisotropic thermal conductivity of nano-porous silica film
(2003)
Tsui, BY
;
Yang, CC
;
Fang, KL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work thermal conductivity of porous silica film was studied comprehensively. Silica films with porosity from 21% to 64% were spin coated. It is observed for the first time that the porous silica material has strong anisotropic characteristic. The pores in the higher porosity silica film tend to distribute horizontally. This distribution of the pores in the dielectric film is the main factor that induces the anisotropic characteristic. We proposed a Serial-Parallel Hybrid model to explain the correlation between porosity and thermal conductivity in both in-plane and cross-plane components. The anisotropic characteristic of the thermal conductivity may be accompanied by the anisotropic dielectric constant, which will greatly complicate the RC delay simulation of the circuits.
Anisotropic thermal conductivity of nanoporous silica film
(2004-01-01)
Tsui, BY
;
Yang, CC
;
Fang, KL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, thermal conductivity of porous silica film with porosity from 21 to 64 % was studied comprehensively. The corresponded dielectric constant is from 2.5 to 1.5. It is observed that the porous silica material has strong anisotropic characteristic. A serial-parallel hybrid model is proposed to explain the correlation between porosity and thermal conductivity in both in-plane and cross-plane components. The pores in the higher porosity silica film tend to distribute horizontally. This distribution of the pores in the dielectric film is the main factor that induces the anisotropic characteristic. The nonuniform distribution of pores also makes the conventional two-dimensional model of 36 method inappropriate for extracting the in-plane thermal conductivity. A new method based on the hybrid model was proposed to extract the in-plane thermal conductivity successfully. The anisotropic characteristic of the thermal conductivity may be accompanied by the anisotropic dielectric constant, which will greatly complicate the thermal management and resistance-capacitance delay simulation of the circuits and should be avoided. The proposed model would be helpful on evaluation of new porous low dielectric constant materials.
Characteristics of Modified-Schottky-Barrier (MSB) FinFETs
(2005)
Lin, CP
;
Tsui, BY
;
電機學院
;
電子工程學系及電子研究所
;
College of Electrical and Computer Engineering
It has been reported that Modified-Schottky-Barrier (MSB) FinFET can solve the problem of low on-state/off-state current ratio that the conventional SB MOSFETs have. In this work, we report for the first time that high performance n- and p-channel MSB devices can be fabricated with the same metal silicide and process technique. Detailed device characteristics as well as hot carrier reliability of MSB FinFETs are investigated. It is concluded that the high performance MSB FinFET is also highly reliable. The simple process and low thermal budget features make the MSB FinFET a very promising nano device.
Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK
(2001-06-01)
Wu, ZC
;
Shiung, ZW
;
Wu, RG
;
Liu, YL
;
Wu, WH
This work investigates the dielectric and barrier properties of two species of organic aromatic low dielectric constant (low-k) polymers, namely, FLARE and SiLK. Experimental results indicate that both of the low-k polymers exhibit acceptable thermal stability with respect to a thermal annealing at 400 degreesC for 8 h in an N-2 ambient. Moreover, they show a good dielectric barrier property against Cu penetration under bias-temperature stressing (BTS) at 150 degreesC with an applied effective field of 0.8 MV/cm. Nevertheless, an anomalous instability of the capacitance-voltage curve was observed for the first time under BTS. This finding is explained by the proposed model of stress induced dielectric polarization charges within these organic aromatic polymers. The polarization instability may seriously degrade the long term reliability of circuit operations. (C) 2001 The Electrochemical Society.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
Electrical and material stability of Orion(TM) CVD ultra low-k dielectric film for copper interconnection
(2002)
Fang, KL
;
Tsui, BY
;
Yang, CC
;
Chen, MC
;
Lee, SD
The electrical and material stability of a newly developed CVD ultra low-k dielectric material called Orion, is explored. It has a dielectric constant of less than 2.2 with excellent thermal stability up to 600degreesC. It shows very low leakage current of only 1nA/cM(2) at 2.5MV/cm. Although both Al and Cu ions can be driven into Orion easily, no metal ions are observed in the Orion with a TAN gate. The Orion material also shows very good adhesion with TaN and oxide hardmask. The current transport mechanism and electrical reliability were investigated. Although weak dielectric polarization occurs under bias-temperature stress, Orion is a very promising material for next generation Cu-interconnect technology.
Electrical characteristics of thin HfO(2) gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH(3) surface nitridation (NH(3)-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO(2) gate dielectrics. The NH(3)-annealed technique is superior to the others because the dielectric subject to NH(3) surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V(inv)), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(R(v)V(inv),). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical characteristics of thin HfO2 gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH3 surface nitridation (NH3-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO2 gate dielectrics. The NH3-annealed technique is superior to the others because the dielectric subject to NH3 surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V-inv), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(RvVinv,). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical reliability issues of integrating low-K dielectrics with Cu metallization
(2000)
Wu, ZC
;
Shiung, ZW
;
Wang, CC
;
Fang, KL
;
Wu, RG
Electrical reliability issues of two organic aromatic low-K materials (K = 2.6 similar to 2.8) were investigated. Both materials show acceptable thermal stability and good dielectric barrier property against Cu penetration. C-V curve instability was observed under bias-temperature stress (BTS) for the first time. It can be explained by the model of stress induced dielectric polarization charges. This instability may be an issue of long term stability of circuits.
Electrical reliability of low dielectric constant diffusion barrier (a-SiC : H) for copper interconnect
(2001)
Fang, KL
;
Tsui, BY
;
Yang, CC
;
Lee, SD
;
電子工程學系及電子研究所
The electrical stability and reliability of the Trimethylsilane (3MS) based a-SiC:H (SIC) film was investigated for the first time. Capacitance-Voltage (C-V) characteristic instability was observed due to polarization at high electrical filed and electron injection at Low electrical field. By adding nitrogen content in the film, the dielectric constant and leakage current are reduced but the time dependent dielectric breakdown (TDDB) lifetime becomes worse at high nitrogen content. It is suggested that the SiC deposition can be optimized at moderate nitrogen content to compromise all film properties.
Electrical stability and reliability of ultralow dielectric constant porous carbon-doped oxide film for copper interconnect
(2005)
Fang, KL
;
Tsui, BY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Nanoporous carbon-doped oxide (CDO) is a promising low dielectric constant (low-k) intermetal dielectric (IMD) for Cu interconnect. The electrical stability and reliability of CDO strongly depend on the contacted metal. An electrical instability model considering metal ion diffusion, dielectric polarization, and carrier injection is proposed for CDO under electrical stress. Both Al and Cu are not suitable for contact with CDO because they can be driven easily into CDO. Fortunately, TaN shows no mobile ion issues when in contact with CDO. The electron transport mechanism is identified to be Schottky emission at low electric field and low temperature. As metal ions are injected into CDO film, the electron transport mechanism changes to Frenkel-Pool emission at high temperature and high electric field. The injection of metal ions into CDO also degrades the time-dependent dielectric breakdown (TDDB) lifetime of CDO. Fortunately, the commonly used diffusion barrier TaN is an excellent contact metal with CDO. The 1-year-long TDDB lifetime allows an electric field stronger than 2 MV/cm, and the TDDB lifetime at 0.5 MV/cm becomes longer than 10 years by several orders of magnitude. It is concluded that the nanoporous CDO is a very promising IMD for next-generation interconnect systems. (c) 2005 The Electrochemical Society.
Formation of interfacial layer during reactive sputtering of hafnium oxide
(2003-06-15)
Tsui, BY
;
Chang, HW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Hafnium oxide is one of the most promising high dielectric constant materials to replace silicon dioxide as the gate dielectric. To take the advantages of high dielectric constant of HfO2 thoroughly, the relatively low dielectric constant interfacial layer must be controlled carefully. In this work, the formation of an interfacial SiO2 layer at the HfO2/Si interface was studied comprehensively. It is observed that during reactive sputtering deposition of the HfO2 layer, a very thick interfacial SiO2 layer, thicker than 3 nm, would be grown. O-radical signals, instead of O-2-radicl signals, are detected in the sputtering chamber. An O-radical enhanced oxidation model is proposed to explain such an unusual thick SiO2 layer. The adoption of a two-step deposition method, the thickness of interfacial SiO2 layer can be reduced only if the bottom Hf layer is thicker than 5 nm. However, the reduction of effective oxide thickness would be limited. Reoxidation of Hf film sounds a better choice. A 1.0-1.5-nm-thick interfacial SiO2 layer is still observed. This implies that the traced oxygen in the sputtering chamber plays a critical role on the formation of the interfacial layer. It is thus concluded that reactive sputtering is not a suitable method to prepare a HfO2 layer with a negligible interfacial SiO2 layer. Reoxidation of Hf film is a better choice, but the oxygen content in the sputtering chamber must be well controlled. (C) 2003 American Institute of Physics.
High thermal stability metal gate with tunable work function
(2004)
Huang, CF
;
Tsui, BY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
It has been reported that the work function of Ta-Pt alloys is tunable and Ta-Pt is a possible gate material for CMOS devices. In this work, we demonstrate that the Ta-Pt alloy is thermally stable up to 900degreesC. The impact of oxygen contamination and thermal stress on the stability of the MOS structure with the alloy gate is also discussed. It is concluded that the Ta-Pt alloy is a good candidate for gate electrode in the nanoscale CMOS regime and is compatible with the conventional self-aligned process.