Browsing by Author "Tsui, Bing-Yue"

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A Comparison Study on the Al-based Interfacial Layers for Ge MIS Devices
(2015)
Yang, Yi-Gin
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The performance of MIS devices on Ge substrate using AlN and Al2O3 as interfacial layer is investigated. Using AlN as interfacial layer can achieve lower leakage current and smaller hysteresis than using Al2O3 because AlN is a more effective barrier to against GeO volatilization and Ge diffusion. However, the interface state density of the AlN/Ge structure is poor. It is found that capping AlN on Al2O3 improves the hysteresis and leakage current while relax the interface state density degradation. It is suggested that appropriate AlN/Al2O3 stack can be used to fabricate high -quality MIS capacitor with ultra-thin effective oxide thickness.
A Comprehensive Evaluation of the Performance of Fin-type Epitaxial Tunnel Layer (ETL) Tunnel FET
(2017-01-01)
Lin, Po-Shao
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Tsui, Bing-Yue
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電機學院
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電子工程學系及電子研究所
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College of Electrical and Computer Engineering
Epitaxial tunnel layer tunnel FET (ETL TFET) is one of the promising device for ultra-low power applications. In this work, device performance between planar ETL TFET and Fin ETL TFET are evaluated. For n-type TFET, the electric field enhancement in Si region due to the fin structure results in Si-to-Ge and Si-to-Si tunneling at low voltage so that the subthreshold swing is degraded. For the p-type TFET, different TFET structures show similar subthreshold swing because only Ge-to-Ge tunneling occurs. In comparison with the planar TFET, Fin TFET exhibits 35% improvement and 40% degradation on conduction current for n-type and p-type TFET, respectively.
A comprehensive study on the oxidation of 4H-SiC in diluted N2O ambient
(2017-04-01)
Tseng, Yuan-Hung
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Wu, Tsung-Han
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Tsui, Bing-Yue
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Yen, Cheng-Tyng
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Hung, Chien-Chung
The oxidation mechanism of 4H-SiC in diluted N2O ambient was studied at various temperatures, N2O flow rates, and N-2/N2O flow ratios. The collision partner, N-2 in this study, plays crucial roles in determining the oxidation rate and N-incorporation. According to the proposed oxidation mechanism, lowering the interface state density at lower oxidation temperatures is possible with a high-efficiency collision partner. (C) 2017 The Japan Society of Applied Physics
A comprehensive study on the oxidation of 4H-SiC in diluted N2O ambient
(2017-04)
Tseng, Yuan-Hung
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Wu, Tsung-Han
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Tsui, Bing-Yue
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Yen, Cheng-Tyng
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Hung, Chien-Chung
The oxidation mechanism of 4H-SiC in diluted N2O ambient was studied at various temperatures, N2O flow rates, and N-2/N2O flow ratios. The collision partner, N-2 in this study, plays crucial roles in determining the oxidation rate and N-incorporation. According to the proposed oxidation mechanism, lowering the interface state density at lower oxidation temperatures is possible with a high-efficiency collision partner. (C) 2017 The Japan Society of Applied Physics
A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH(3) Plasma Treatment
(2010-07-01)
Lee, Chen-Ming
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel 30-nm gate-all-around (GAA) polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistor (TFT) is reported for the first time. Owing to the NW and GAA structure, the channel electric potential is well controlled by the gate electrode. After NH(3) plasma treatment for defects passivation, the values of 0.97 V, 224 mV/dec., and 0.895 V/V of threshold voltage, subthreshold swing, and drain-induced barrier lowering are achieved, respectively. A high driving current of 459 mu A/mu m and an ON-state/OFF-state current ratio of 5 x 10(7) are also obtained. These excellent characteristics indicate that the ultrasmall GAA NW poly-Si TFT would have the potential to be applied in the 3-D integrated-circuit or system-on-panel field.
A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH3 Plasma Treatment
(2010-07-01)
Lee, Chen-Ming
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel 30-nm gate-all-around (GAA) polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistor (TFT) is reported for the first time. Owing to the NW and GAA structure, the channel electric potential is well controlled by the gate electrode. After NH3 plasma treatment for defects passivation, the values of 0.97 V, 224 mV/dec., and 0.895 V/V of threshold voltage, subthreshold swing, and drain-induced barrier lowering are achieved, respectively. A high driving current of 459 mu A/mu m and an ON-state/OFF-state current ratio of 5 x 10(7) are also obtained. These excellent characteristics indicate that the ultrasmall GAA NW poly-Si TFT would have the potential to be applied in the 3-D integrated-circuit or system-on-panel field.
A New Procedure to Extract Ultra-Low Specific Contact Resistivity
(2012)
Tseng, Hsuan-Tzu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this work, a new procedure to extract ultra-low specific contact resistivity down to 10(-9) Omega-cm(2) is proposed. Design guidelines of the test structure are analyzed with 3-D simulation. Compared to the typical Cross-bridge-Kelvin resistor structure, the proposed structure has much better accuracy at low resistivity regime, looser design rules, simpler fabrication process.
A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells
(2015-08-01)
Wang, Pei-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (V-T) induced by the discrete grain-boundary traps are studied. Various Delta V-T behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Delta V-T is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of V-T in 3-D VG memory cells.
A process for high yield and high performance carbon nanotube field effect transistors
(2010-05-01)
Lee, Tseng-Chin
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Tsui, Bing-Yue
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Tzeng, Pei-Jer
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Wang, Ching-Chiun
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Tsai, Ming-Jinn
Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 mu S, and high I(on)/I(off) ratio of 10(6) can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. (C) 2010 Elsevier Ltd. All rights reserved.
A Reliable Schottky Barrier Height Extraction Procedure
(2016)
Tsui, Bing-Yue
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Fu, Tze-Yu
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電機學院
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電子工程學系及電子研究所
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College of Electrical and Computer Engineering
This work proposes a Schottky barrier extraction procedure which considers the thermionic field emission (TFE) model, image-force induced barrier lowering effect, and parasitic resistance. The accuracy of the Schottky barrier height extracted by the field emission (FE) model at forward bias and the TFE model at reverse bias is evaluated. The TFE model can obtain accurate SBH with low SBH (similar to 0.3 eV) and high doping concentration (similar to 1x10(20) cm(-3)). It is thus recommended that the proposed extraction procedure could be used to study the Schottky junction precisely.
A study on NiGe-contacted Ge n(+)/p Ge shallow junction prepared by dopant segregation technique
(2015-05-01)
Tsui, Bing-Yue
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Shih, Jhe-Ju
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Lin, Han-Chi
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Lin, Chiung-Yuan
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電子工程學系及電子研究所
In this work, the effect of dopant segregation on the NiGe/n-Ge contact is studied by experiments and first-principles calculations. Both Al-contacted and NiGe-contacted n(+)/p junctions were fabricated. Phosphorus and arsenic ions were Implanted Before Germanide (IBG) formation or Implanted After Germanide (IAG) formation. The NiGe-contacted junction always exhibit higher forward current than the Al-contacted junction due to dopant segregation. First principles calculations predict that phosphorus atoms tend to segregate on both NiGe side and Ge side while arsenic atoms tend to segregate at Ge side. Since phosphorus has higher activation level and lower diffusion coefficient than arsenic, we propose a phosphorus IBG + arsenic IAG process. Shallow n(+)/p junction with junction depth 90 nm below the NiGe/Ge interface is achieved. The lowest and average contact resistivity is 2 x 10(-6) Omega cm(2) and 6.7 x 10(-6) Omega cm(2), respectively. Methods which can further reduce the junction depth and contact resistivity are suggested. (C) 2015 Elsevier Ltd. All rights reserved.
Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
(2016-01-01)
Wang, Pei-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.
Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
(2016-01)
Wang, Pei-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.
Bandgap engineering of Si1-xGex epitaxial tunnel layer for tunnel FETs
(2018-08-01)
Chen, Yi-Ju
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The effects of the Si-1-xGe(x) epitaxial tunnel layer (ETL) scheme and ETL thickness on the ON-state current (l(ON)) of Si-1_Ge-x(x) ETL tunnel field-effect transistors (TFETs) are thoroughly studied in this work. Compared with using pure Ge as the ETL, implementing Si1-xGex with linearly changing Ge content degrades l(ON) markedly, whereas using Si1-xGex with stepwise changing Ge content degrades l(ON) slightly. Although changing the ETL material from Ge to Si1-xGex leads to l(ON) reduction, for practical implementation, it is anticipated that a better subthreshold swing (SS) can be obtained by ETL crystal quality improvement. The best Si1-xGex ETL scheme for application in complementary Si1-xGex ETL TFETs is 4-nm-thick Si1-xGex with stepwise decreasing bandgap (E-g).( )It is believed that this structure is more promising for implementation. (C) 2018 The Japan Society of Applied Physics.
Bias-Dependent Source Injection Resistance of Modified Schottky Barrier MOSFET
(2008)
Tsui, Bing-Yue
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Lu, Chi-Pei
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Liu, Hsiao-Han
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Modified Schottky Barrier MOSFET with low resistance metal source/drain and good short channel effect immunity is one of the promising nano-scale device structures. In this work, a modified external load resistance method was proposed to extract the bias dependent source injection resistance of the MSB multi-gate MOSFET. The injection resistance is exponentially proportional to (V(GS)-V(th)-0.5V(DS)) and would be close to the source/drain resistance of conventional MOSFET at high gate bias.
Characteristics of size dependent conductivity of the CNT-interconnects formed by low temperature process
(2013-06-01)
Chiu, Wei-Chih
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a simple and low temperature fabrication process, slow spin rate coating and dry etching, is proposed to construct the CNT-interconnects for future VLSI interconnect applications. Two sets of CNT-interconnects named width and length varying interconnects were fabricated to investigate the characterization of size dependent conductivity of CNT-interconnects. Not only the amount of the CNT solution spin-coated for forming the CNT networks but also the area of CNT-interconnect regime would affect the conductance, variation, and conductive probability of CNT-interconnects. The yield of working CNT-interconnects does not show direct relation with the conductive probability or the amount of the CNT solution for CNT network formation. Based on the percolation theory, we characterize the average conductance of size-varying CNT-interconnects by three regions: percolation region, power region and linear region. In addition, as the density within a specified CNT-interconnect regime accumulates, the conductive behavior would be eventually characterized as a conventional resistor. (C) 2013 Elsevier Ltd. All rights reserved.
Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation
(2017-06-01)
Tseng, Yuan-Hung
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Lin, Chung-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letterwould be insightful for silicon-carbide-basedvery-large-scale integration technology.
Current transport mechanisms of Schottky barrier and modified schottky barrier MOSFETs
(2007)
Tsui, Bing-Yue
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Lu, Chi-Pei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Current transport mechanisms of Schottky barrier (SB) and Modified Schottky barrier (MSB) MOSFETs are investigated by measuring the temperature effect on current-voltage characteristics. For SB MOSFETs, current transport could be dominated by thermionic emission or tunneling mechanism depends on the Schottky barrier height and the gate voltage. The current transport of the MSB MOSFETs changes from tunneling mechanism to drift-diffusion mechanism as the gate voltage increases. The changing point is a good indicator to evaluate the efficiency of the MSB junction. Since the current transport mechanism depends on bias condition, the extraction of mobility should be treated carefully, especially at low gate voltage.
Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer
(2020-03-01)
Tsui, Bing-Yue
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Liao, Hsiu-Hsien
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Chen, Yi-Ju
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this article, the degradation mechanism of the Ge N+-P junctions with a thin GeSn surface layer is investigated, aiming for source/drain (S/D) application in emerging field-effect transistors. GeSn is a promising channel material with high carrier mobility, which can offer a better performance of the field-effect transistors. By performing thermal annealing at different temperatures, the reverse-biased leakage current increases apparently when annealing temperature exceeds 550 degrees C. X-ray diffraction (XRD) analysis indicates most Sn atoms escape from lattice sites while secondary-ion mass spectroscopy (SIMS) analysis indicates enhanced Sn diffusion in Ge bulk after ion implantation. Therefore, a degradation model considering Sn-defects interaction is proposed to explain the degradation of junction leakage current and possible solution is proposed.
Effect of Formation Temperature on Quality of Gate Dielectric on Germanium Substrate
(2016)
Wei, Erh-Jye
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Tsui, Bing-Yue
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Wu, Pin-Jiun
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加速器光源科技與應用學位學程
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電子工程學系及電子研究所
Germanium metal-insulator-semiconductor (MIS) structure with HfO2/Al2O3/GeO2 gate stack have been demonstrated to exhibit good performance. In this work, the effect of formation temperature of the gate stack on the quality of the gate dielectric is investigated. It is found that the higher plasma oxidation temperature helps the GeO2 formation and less interface states. But the higher deposition temperature of the ALD high-k films may degrade the interface and result in higher leakage current.