Browsing by Author "Tu, CH"

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A novel method for growing polycrystalline Ge layer by using UHVCVD
(2006-02-24)
Tu, CH
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Chang, TC
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Liu, PT
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Yang, TH
;
Zan, HW
Poly-Ge grown on SiO2 substrates by using one-step ultra-high vacuum chemical vapor deposition (UHVCVD) process with thin Si nucleation layers at very low deposition temperature (350 degrees C) was demonstrated. The results demonstrated that the polycrystalline silicon (poly-Si) nucleation layer is needed for the growth of polycrystalline germanium (poly-Ge) on SiO2 substrates at low growth temperature. SEM image presents the films with uniform rain size and uniform thickness occurring in the samples. The grain size of poly-Ge is about 100 nm. The Raman shift spectrum and XRD spectrum also identified that films are high quality poly-Ge by using this method. (c) 2005 Elsevier B.V. All rights reserved.
Characteristics and stress-induced degradation of laser-activated low temperature polycrystalline silicon thin-film transistors
(2003-02-15)
Peng, DZ
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Chang, TC
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Chang, CY
;
Tsai, ML
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Tu, CH
The characteristics and reliability of laser-activated polycrystalline silicon thin-film transistors (poly-Si TFTs) under the stress condition of drain voltage (V-d)=12 V and gate voltage (V-g)=15 V have been investigated. In spite of reducing the source/drain resistivity by using laser activation method, the leakage current (V-g<0) is larger for laser-activated poly-Si TFTs in comparison with traditional furnace-activated counterparts. It is also found that the post-stress leakage and on/off current ratio degrade much faster for laser-activated poly-Si TFTs, while the degradation rates of threshold voltage and subthreshold swing are comparable to those of traditional furnace-activated TFTs. The laser activation modifies the grain structure between drain and channel region and causes grain discontinuity extending from the drain side to the channel region. The grain discontinuity near drain side in the polysilicon film has been investigated by transmission electron microscopy analysis. The effective trap state density calculated from typical I-V curve has been compared for laser-activated and furnace-activated TFTs. As a result, an inferior reliability with extra trap state density and larger leakage current was observed in the laser-activated poly-Si TFTs. (C) 2003 American Institute of Physics.
Effects of channel width and NH3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization
(2005)
Wu, YC
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Chang, TC
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Chou, CW
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Wu, YC
;
Liu, PT
This work studied the effects of channel width and NH3 plasma passivation on the electrical characteristics of a series of pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs). The performance of PDMILC TFTs improves as each channel width decreasing. Further, PDMILC TFTs with NH3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nanoscale TFT with ten 67 nm wide split channels (M10) are superior to those of other TFTs. The former includes a higher field effect mobility of 84.63 cm(2)/V s, a higher ON/OFF current ratio (> 10(6)), a steeper subthreshold slope (SS) of 230 mV/decade, and an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit the most poly-Si grain enhanced to reduce the grain boundary defects and the best NH3 plasma passivation. Both effects can reduce the number of defects at grain boundaries of poly-Si in active regions for high performances. (c) 2005 The Electrochemical Society. All rights reserved.
Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels
(2005-10-01)
Wu, YC
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Chang, TC
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Liu, PT
;
Chen, CS
;
Tu, CH
This brief studies the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly doped drain (LDD) structures. The nanoscale TFT with ten 67-nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with each channel width decreasing, yielding a profile from a single-gate to tri-gate structure.
Enhanced performance of poly-Si thin film transistors using fluorine ions implantation
(2005)
Tu, CH
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Chang, TC
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Liu, PT
;
Zan, HW
;
Tai, YH
Fluorine (F)-implanted polycrystalline silicon thin-film transistor (poly-Si TFT) are proposed for the enhancement of device performance. A significant improvement in electrical characteristics, such as I-ON/I-OFF ratio, and field effect mobility, can be realized in the new thin-film transistor. The field effect mobility for F-implanted poly-Si TFTs is 53.82 cm(2)/V-s, and higher than 19.74 cm(2)/V-s in conventional SPC poly-Si TFTs. Furthermore, the F-implanted poly- Si TFT exhibits high immunity against hot carrier effect and improved electrical reliability. The manufacturing processes are simple and without additional thermal annealing steps, thereby compatible with the conventional TFT fabrication processes. (c) 2005 The Electrochemical Society. All rights reserved.
Formation of silicon germanium nitride layer with distributed charge storage elements
(2006-03-13)
Tu, CH
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Chang, TC
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Liu, PT
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Liu, HC
;
Chen, WR
The formation of silicon germanium nitride (SiGeN) with distributed charge storage elements is proposed in this work. A large memory window is observed due to the retainable dangling bonds inside the SiGeN gate stack layer. The nonvolatile memory device with the high-temperature oxidized SiGeN stack layer exhibits 2 V threshold voltage shift under 7 V write operation, which is sufficient for a memory device to define the signal "0" and "1." Also, the manufacture technology using the sequent high-temperature oxidation of the a-Si layer acting as the blocking oxide is proposed to enhance the performance of nonvolatile memory devices. (c) 2006 American Institute of Physics.
High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels
(2004)
Wu, YC
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Chang, CY
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Chang, TC
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Liu, PT
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Chen, CS
We have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH3 plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (>10(9)), a steep subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability.
High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates
(2006-05-01)
Wu, YC
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Chang, TC
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Liu, PT
;
Chou, CW
;
Wu, YC
In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V-th) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.
High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure
(2004-05-10)
Wu, YC
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Chang, TC
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Chang, CY
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Chen, CS
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Tu, CH
This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (>10(8)), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies. (C) 2004 American Institute of Physics.
Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC
(2006-04-01)
Tu, CH
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Chang, TC
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Liu, PT
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Yang, CY
;
Liu, HC
The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.
Improvement of reliability for polycrystalline thin-film transistors using self-aligned fluorinated silica glass spacers
(2005)
Tu, CH
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Chang, TC
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Liu, PT
;
Zan, HW
;
Tai, YH
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with self-aligned fluorine-doped SiO2 (FSG) spacer were investigated in this study. The presence of FSG spacers can effectively reduce the lateral electrical field near the drain side of a poly-Si TFT device, and strongly passivate Si dangling bonds at the grain boundaries. The significant enhancement in electrical performance suppresses serious kink effect and improves electrical reliability of poly-Si TFTs effectively. In addition, the proposed poly-TFT structure is uncomplicated and compatible with existing TFT manufacturing processes. (c) 2005 The Electrochemical Society.
Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization
(2005-10-03)
Wu, YC
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Chang, TC
;
Liu, PT
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Wu, YC
;
Chou, CW
This work presents a method for enhancing the mobility of polycrystalline-Si (poly-Si) thin-film transistors (TFTs) by pattern-dependent metal-induced-lateral-crystallization (PDMILC) using nanowire channels. Experimental results indicate that the field-effect mobility of PDMILC TFT was enhanced as the channel width decreased, because the lateral length of the poly-Si grains increased. The PDMILC poly-Si TFT with ten nanowire channels (M10) had the greatest field-effect mobility, 109.34 cm(2)/V s and the lowest subthreshold swing, 0.23 V/dec, at a gate length of 2 mu m. The field-effect mobility also increased as the gate length in the M10 PDMILC poly-Si TFT device declined, because the number of poly-Si grain-boundary defects was reduced. (C) 2005 American Institute of Physics.
Moisture-induced material instability of porous organosilicate glass
(2003-04-01)
Chang, TC
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Chen, CW
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Liu, PT
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Mor, YS
;
Tsai, HM
The mechanism of leakage current of porous organosilicate glass (POSG) with O-2 plasma ashing is investigated. The O-2 plasma ashing often deteriorates the POSG film, causing moisture uptake. We find that the leakage-current mechanism of POSG transforms from Schottky emission into ionic conduction after O-2 plasma treatment. The mobile ions (H+,OH-) supported by absorbing moisture move easily when an external electric field is applied to POSG film, which leads to the ionic conduction leakage current across the moisture-absorbing POSG film. Hence, the leakage current density is drastically increased about four to five orders of magnitude compared with untreated POSG film. (C) 2003 The Electrochemical Society.
Reduction of leakage current in metal-induced lateral crystallization polysilicon TFTs with dual-gate and multiple nanowire channels
(2005-09-01)
Wu, YC
;
Chang, TC
;
Liu, PT
;
Chou, CW
;
Wu, YC
This letter addresses the leakage current in nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with multiple nanowire channels and dual-gate. Experimental results reveal that applying multiple nanowire channels improves the Ni-MILC poly-Si TFT performance. However, the leakage current of both single-gate with single-channel and multiple nanowire channels remains high (> 10(-8) A), because of the field emission of carriers through the poly-Si grain traps and the defects caused by Ni contamination. Applying the dual-gate structure can suppress the electrical filed in the drain depletion region, significantly reducing the leakage current of the Ni-MILC poly-Si TFT, increasing the ON/OFF ratio.