Browsing by Author "Tu, SW"

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Inductance modeling for on-chip interconnects
(2002)
Tu, SW
;
Shen, WZ
;
Chang, YW
;
Chen, TC
;
電子工程學系及電子研究所
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable. to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [11] is within 10% for practical cases.
Inductance modeling for on-chip interconnects
(2003-04-01)
Tu, SW
;
Shen, WZ
;
Chang, YW
;
Chen, TC
;
Jou, JY
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout ( placement and routing) tool for inductance ( delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.
Layout techniques for on-chip interconnect inductance reduction
(2004)
Tu, SW
;
Jou, JY
;
Chang, YW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques ground-aware net routing and source pin positioning that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry [7] to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.
On-chip bus encoding for LC cross-talk reduction
(2005)
Huang, JS
;
Tu, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, as the working frequency of integrated circuits increasing above GHz, the inductive crosstalk will also have very significant influence on the global interconnect delay. However, most existing works consider only RC effects (the worst-case switching pattern resulting from coupling capacitance), to develop their encoding schemes to reduce bus delay. In this paper, we propose a flexible bus encoding method to reduce the LC coupling delay on on-chip bus with a user-given bus structure, the working frequency, and the delay constraint. Simulation results show that our encoding method can significantly reduce the coupling delay of a bus according to the delay constraint.
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
(2005)
Tu, SW
;
Jou, JY
;
Chang, YW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Inductance effects of on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. ne finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.
RLC effects on worst-case switching pattern for on-chip buses
(2004)
Tu, SW
;
Jou, JY
;
Chang, YW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Inductance effects on on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially on global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we show that the worst-case switching patterns that incur the largest bus delay are completely different while considering RC and RLC effects. The finding implies that existing encoding schemes based on RC model might not improve or even worsen the bus delay when inductance effects become dominant.