Browsing by Author "Tu, Shang-Wei"

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On-chip bus encoding for power minimization under delay constraint
(2007)
Lin, Tzu-Wei
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Tu, Shang-Wei
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Jou, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As technology advances, the global interconnect delay and the power consumption of long wires become crucial issues in nanometer technologies. In particular, both inductive and capacitive coupling effects between wires result in serious problems such as crosstalk delay, coupling noise, and power consumption. In this paper, we propose a new bus encoding scheme for global bus design in nanometer technologies. With the user-given bus parameters, the working frequency, and the delay constraint, the scheme can minimize the bus power consumption subject to the delay constraint by effectively reducing the LC coupling effects.
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
(2006-10-01)
Tu, Shang-Wei
;
Chang, Yao-Wen
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Jou, Jing-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper shows. that the worst case switching pattern that incurs the longest bus delay While considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses.