Browsing by Author "Tuan, JC"

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An architecture of full-search block matching for minimum memory bandwidth requirement
(1998)
Tuan, JC
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper art architecture of full-search block matching motion estimation suitable for high qualify video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth wilt increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford it, This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done bf setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value only little overhead is introduced. Due to the reduction of memory bandwidth, the costs of frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency if still achieved Simple and regular interconnections is featured to ensure high speed operation by an efficient and distributed local memory organization.
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
(2002-01-01)
Tuan, JC
;
Chang, TS
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work explores the data reuse properties of full-search block-matching (FSBM) for motion estimation (NEE) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, memory bandwidth in ME is analyzed and the problem is solved by exploring data reuse. Four levels are defined according to the degree of data reuse for previous frame access. With the highest level of data reuse, one-access for frame pixels is achieved. A scheduling strategy is also applied to data reuse of ME architecture designs and a seven-type classification system is developed that can accommodate most published ME architectures. This classification can simplify the work of designers in designing more cost-effective ME architectures, while simultaneously minimizing memory bandwidth. Finally, a FSBM architecture suitable for high quality HDTV video with a minimum memory bandwidth feature is proposed. Our architecture is able to achieve 100% hardware efficiency while preserving minimum I/O pin count, low local memory size, and bandwidth.