Browsing by Author "Tung, Jonathan"

Now showing 1 - 1 of 1

Statistical Techniques for Predicting System-Level Failure using Stress-Test Data
(2015)
Chen, Harry H.
;
Kuo, Shih-Hua
;
Tung, Jonathan
;
Chao, Mango C. -T.
;
電子工程學系及電子研究所
In this paper we describe a novel scheme for collecting and analyzing a chip\'s failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip\'s "analog" failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.