Browsing by Author "Tung, SW"

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A logical fault model for library coherence checking
(1998-09-01)
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A library is the basis of modularized design now. Most operations of CAD tools are based on cell definitions in a library. In this paper, we first give a definition of a library and describe the complexity of library verification. A unified automatic test pattern generation and verification environment is then proposed. The amount of library data coherence checking is reduced to functional simulation on different views of the cells. In order to reduce the number of lest vectors and the amount of simulation time, a Port Order Fault (POF) model is proposed. Using the POF model and the sensitized path approach [1] to generate test vectors, the proposed approach could effectively reduce the complexity of the functional test vectors from O(2(n)) to O(n) for cells with n inputs. Using the POF model, the test sequence can also detect timing inconsistency under the verification environment.
An automatic interconnection rectification technique for SoC design integration
(2003)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an automatic interconnection rectification (AIR) technique to correct the misplaced interconnection occurred in the integration of a SoC design automatically. The experimental results show that the AIR can correct the misplaced interconnection and therefore accelerates the integration verification of a SoC design.
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
(2002-10-01)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45 % smaller and the run time decreases 16 % as compared with the previous results of AVPG.
An improved AVPG algorithm for SoC design verification using port order fault model
(2001)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in the design of large System-on-a-Chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator To reduce the verification complexity, the Port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been developed [2] [3]. Here we present in automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) proposed in [3] for SoC design verification based on POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.
Automatic interconnection rectification for SoC design verification based on the port order fault model
(2003-01-01)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.
On automatic-verification pattern generation for SoC with port-order fault model
(2002-04-01)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in the designs of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tung and Jon, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage.
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model
(2001)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in the design of large System-on-a-Chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator To reduce the verification complexity, the port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been developed [2] [3]. Adders and multipliers are the most often used data path elements in core-based designs. Due to their regularity, the development of the verification pattern sets can be achieved in a systematic method In this paper, we present the algorithms of generating the minimum. verification pattern sets for adders and multipliers and these pattern sets are much smaller than that obtained from the automatic verification pattern generation (AVPG) proposed in [3].
SOC design integration by using automatic interconnection rectification
(2003)
Wang, CY
;
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an automatic interconnection rectification (AIR) technique to correct the misplaced interconnection occurred in the integration of a SoC design automatically. The experimental results show that the AIR can correct the misplaced interconnection and therefore accelerates the integration verification of a SoC design.