Browsing by Author "Van, Lan-Da"

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2-D Digital Filter Architectures without Global Broadcast and Some Symmetry Applications
(2009)
Khoo, I-Hung
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Reddy, Hari C.
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Van, Lan-Da
;
Lin, Chin-Teng
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資訊工程學系
Four new 2-D filter VLSI architectures without global broadcast are presented. The first is a transposed systolic structure which requires fewer delay elements compared to the original systolic structure in [1]. By combining the sub-blocks of the original with the new transposed structure, two additional systolic structures are obtained to realize transfer functions with separable denominators, which require fewer multipliers. These separable denominator structures have important symmetry applications. A structure which possesses diagonal symmetry is then shown which requires even fewer multipliers.
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications
(2011)
Lu, Tsung-Che
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Van, Lan-Da
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Lin, Chi-Sheng
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Huang, Chun-Ming
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資訊工程學系
A low-FOM SAR ADC using the leakage reduction bootstrapped switch (LRBS) to achieve a satisfactory ENOB and using a low-power approach with a low voltage, low sampling rate, and low-DAC-capacitance structure is presented for biomedical applications. LRBS is proposed to alleviate the leakage caused by the low-power approach to increase SNDR and ENOB. From the measurement results, the 0.18 mu m CMOS prototype chip with the total DAC capacitance of 2.765pF consumes 2.5nW and achieves a SNDR of 53.05dB under a 0.5V supply voltage at 1KS/s with a Nyquist input. The resulting FOM is 6.8fJ/conversion-step.
A Grouped-Iterative Framework for MIMO Detection
(2008)
Wu, Di-You
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Van, Lan-Da
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資訊工程學系
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Department of Computer Science
In this paper, we propose one grouped-iterative framework to generate a family of the MIMO detection algorithms. The presented framework not only includes the conventional iterative, grouped, and Chase detection algorithms, but also derives a new low-complexity MIMO detection algorithm. The proposed detection can adjust some parameters to achieve a range of trade-offs between performance and complexity. In (4,4) system with uncoded 16-QAM inputs, one instance of the proposed detection algorithm not only substantially reduces the multiplication complexity by 26.3% but also outperforms the BODF algorithm about 5dB. Another instance of the proposed algorithm can save multiplication complexity by 34% at the penalty of 1 dB loss compared with the B-Chase detector.
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
(2006)
Lin, Chin-Teng
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Yu, Yuan-Chu
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Van, Lan-Da
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資訊工程學系
;
電控工程研究所
In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT (R8-FFT) unit and an efficienet data-swapping method based output buffer unit The whole chip systematic performance concerning about the area, power, latency and pending cycles for the application of IEEE 802.11a WLAN standard has been analyzed. The proposed R8-FFT unit utilizing the symmetry property of the matrix decomposition achieves half computation-complexity and less power consumption compared with the recently proposed FFT/IFFT designs, On the other hand, applying the proposed data-swapping method, a low-cost and low-power output buffer can be obtained, So as to further increase system performance, we propose one scheme: the multiplication-after-write (MA K) method. Applying MAW method with R8-FFT unit, the resulting FFT/IFFT design not only leads to the balancing pending cycle, but also abbreviating computation latency to 8 clock cycles. Consequently, adopting the above proposed two units and one scheme, the whole chip consumes 22.36mW under 1.2V@20 MHz in TSMC 0.13 1P8M CMOS process.
A New VLSI 2-D Diagonal-Symmetry Filter Architecture Design
(2008)
Chen, Pei-Yu
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Van, Lan-Da
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Reddy, Hari C.
;
Lin, Chin-Teng
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資訊工程學系
In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.
A New VLSI 2-D Fourfold-Rotational-Symmetry Filter Architecture Design
(2009)
Chen, Pei-Yu
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Van, Lan-Da
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Reddy, Hari C.
;
Lin, Chin-Teng
;
資訊工程學系
In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function using fourfold rotational symmetry. The presented type-I structure with fourfold rotational symmetry has the lowest number of multipliers, and zero latency. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System
(2011-09-01)
Van, Lan-Da
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Sheu, Ten-Yao
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資訊工程學系
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Department of Computer Science
In this paper, a power-area efficient geometry engine (GE) using a low-complexity three-level subdivision algorithm is presented. The proposed subdivision algorithm and architecture is capable of providing low complexity, high power-area efficiency, scalable and near-Phong shading quality. The forward difference, edge function recovery, dual space subdivision, triangle filtering, and triangle setup coefficient sharing schemes are employed to alleviate the redundant computation for the proposed algorithm. According to the low-complexity subdivision algorithm, one reconfigurable datapath is proposed to save the area since the same set of processing elements (PE) is reused for different operations of GE. Compared with the conventional subdivision algorithm, the proposed subdivision algorithm reduces the number of memory/register accesses for subdivision by 40% and 60.32% for level-1 and level-2 subdivision, respectively. In terms of the number of multiplications for transforms, the reduction can be attained by 27.5% and 60.27% for level-1 and level-2 subdivision, respectively. From the implementation results, the proposed GE can achieve the power-area efficiency of 518.8 K vertices/(s.mW.mm(2)) for level-1 subdivision.
A Special Section on Advanced Signal Processing Technologies and Systems for Healthcare Applications
(2015-04-01)
Zhang, Zhiguo
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Van, Lan-Da
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資訊工程學系
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Department of Computer Science
Adaptive low-error fixed-width booth multipliers
(2007-06-01)
Song, Min-An
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Van, Lan-Da
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Kuo, Sy-Yen
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資訊工程學系
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Department of Computer Science
In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65-84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.
An Intelligent Elevator Development and Management System
(2020-06-01)
Van, Lan-Da
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Lin, Yi-Bing
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Wu, Tsung-Han
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Lin, Yu-Chi
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資訊工程學系
This paper proposes ElevatorTalk, an elevator development and management system based on the Internet of Things (IoT) approach called IoTtalk. This system modularizes the software into elevator components so that we can develop flexible and scalable car scheduling algorithms. ElevatorTalk consists of three subsystems: cars, scheduler, and the elevator car operating (ECO) panel. The first two subsystems are used to develop the elevator systems, and the third subsystem is used to receive requests issued by the passengers. These three subsystems work in parallel, and communicate with each other through sending and receiving messages. ElevatorTalk can connect to a real elevator system to serve as the elevator management center. It can also emulate the existing elevator systems with different car scheduling algorithms. We propose an intelligent aggressive car scheduling with initial car distribution (ACSICD) algorithm in ElevatorTalk. Our paper indicates that ACSICD has better waiting/travel/journey time performance and/or accuracy than the previous proposed algorithms. We also show that in our approach, the car scheduling decision can be quickly made with 0.2010 ms, and therefore good performance in the time complexity is achieved.
Analyzing Students' Attention in Class Using Wearable Devices
(2017-01-01)
Zhang, Xin
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Wu, Cheng-Wei
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Fournier-Viger, Philippe
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Van, Lan-Da
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Tseng, Yu-Chee
Detecting students' attention in class provides key information to teachers to capture and retain students' attention. Traditionally, such information is collected manually by human observers. Wearable devices, which have received a lot of attention recently, are rarely discussed in this field. In view of this, we propose a multimodal system which integrates a head-motion module, a pen-motion module, and a visual-focus module to accurately analyze students' attention levels in class. These modules collect information via cameras, accelerometers, and gyroscopes integrated in wearable devices to recognize students' behaviors. From these behaviors, attention levels are inferred for various time periods using a rule-based approach and a data-driven approach. The former infers a student's attention states using user-defined rules, while the latter relies on hidden relationships in the data. Extensive experimental results show that the proposed system has excellent performance and high accuracy. To the best of our knowledge, this is the first study on attention level inference in class using wearable devices. The outcome of this research has the potential of greatly increasing teaching and learning efficiency in class.
Anticipatory access pipeline design for phased cache
(2008)
Hsueh, Chih-Wen
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Chung, Jen-Feng
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Van, Lan-Da
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Lin, Chin-Teng
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電控工程研究所
For an embedded processor, the cache design almost occupies half chip area and power consumption. According to Amdahl's law, if the power consumption of cache memories is reduced, the embedded processor can significantly save much power. However, the cache misses result in the penalty of thousands of cycles waiting and power consumption due to increasing the number of external memory access. Based on the above reason, the phased cache design is proposed and can largely improve the power consumption which wastes a set-associative cache. In this paper, the embedded pipelining processor without stalling and low-power phase cache is practiced with high-level simulation to achieve high-performance and low-power design. As experimental results, the proposed phase cache can reduce 44% power consumption compared with traditional one-access-cycle cache and eliminate pipeline stalls incurred by phased cache with only 6% gate count overhead.
Area-Efficient 2-D Digital Filter Architectures Possessing Diagonal and Four-Fold Rotational Symmetries
(2013-01-01)
Chen, Pei-Yu
;
Van, Lan-Da
;
Reddy, Hari C.
;
Khoo, I-Hung
;
交大名義發表
In this paper, two area-efficient two-dimensional (2-D) IIR filter architectures for 2-D transfer function with diagonal and four-fold rotational symmetries are proposed for image processing. For this purpose, two different intermediate transfer functions are applied and the corresponding two new filter architectures are obtained. Under satisfactory average error performance, we determine that the new filter structure requires less multiplier wordlength than the previously published Type-1 filter structure. With the features of less numerator multiplier wordlength and shorter critical path, the proposed diagonal and four-fold rotational symmetry filter architectures can result in 10.17% and 3.35% area reduction with respect to the published Type-1 IIR filter structures with diagonal and four-fold rotational symmetries in terms of synthesis results.
Classification of driver's cognitive responses using nonparametric single-trial EEG analysis
(2007)
Lin, Chin-Teng
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Ko, Li-Wei
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Lin, Ken-Li
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Kuo, Bor-Chen
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Liang, Sheng-Fu
Accidents caused by errors and failures in human performance among traffic fatalities have a high rate causing death and become an important issue in public security. The key problem causing these car accidents is mainly because that the drivers failed to perceive the changes of the traffic lights or the unexpected conditions happening accidentally on the roads. In this paper, we devised a quantitative analysis for ongoing assessment of driver's cognitive responses by investigating the neurobiological information underlying electroencephalographic (EEG) brain dynamics in traffic-fight experiments in a virtual-reality (VR) dynamic driving environment. Three different feature extraction methods including Nonparametric Weighted Feature Extraction (NWFE), Principlal Component Analysis (PCA), Discriminant Analysis Feature Extraction (DAFE) are applied to reduce the feature dimension and project the measured EEG signals to a feature space spanned by their eigenvectors. After that, the mapped data can be classified with fewer features and their classification results are compared by utilizing three different classifiers including Gaussian classifier (GC), k Nearest neighbor classification (KNNC), and Naive Bayes Classifier (NBC). Experimental results show that the successful rate of Nonparametric Weighted Feature Extraction combined with Gaussian classifier is higher more than 10% compared with other combinations. It also demonstrates the feasibility of detecting and analyzing single-trail ERP signals that represent operators' cognitive states and responses to task events.
Continuous Human Location and Posture Tracking by Multiple Depth Sensors
(2014)
Qiu, Jun-Wei
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Chiang, Ting-Hui
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Lo, Chi Chung
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Lin, Li-Min
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Van, Lan-Da
This paper proposes a continuous location and skeletal tracking system using multiple RGB-Depth sensors (such as Kinects) deployed along a corridor with overlapping coverages. First, we transform the coordinates of all sensor into a unified coordinate. Second, the system recognizes users (such as patients under rehabilitation) from different views of these sensors and classifies them by their patient IDs. Third, the patient information can be continuously handed over among sensors when they move around the area. Experiment results show that the skeletal association during handover achieves approximately 90.61% in accuracy and 96.89% in precision in 44,817 experiment trials. By our observation, injured people possess asymmetric gait parameters especially on the ratio of the duration of the swing/stance phase. For example, the injured foot generally has a longer swinging duration than the healthy side. The proposed system has potential in patient rehabilitation monitoring applications.
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing
(2016-01-01)
Van, Lan-Da
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Huang, Po-Yen
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Lu, Tsung-Che
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資訊工程學系
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Department of Computer Science
This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU1 and PU2, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU1 is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm(2). From the experimental results, the presented work achieves satisfactory performance for each function.
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
(2008-08-01)
Lin, Chin-Teng
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Yu, Yuan-Chu
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Van, Lan-Da
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資訊工程學系
;
電機學院
This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
(2008-08-01)
Lin, Chin-Teng
;
Yu, Yuan-Chu
;
Van, Lan-Da
;
資訊工程學系
;
電機學院
This investigation proposes a novel radix-4(2) algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4(2) single delay feedback path (R4(2)SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8 x 8 2-D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8 x 8 2-D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 x 8 2-D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2-D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mu m CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.
Demo: Tagging IoT Data in a Drone View
(2019-01-01)
Van, Lan-Da
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Chang, Chun-Hao
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Tong, Kit-Lun
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Wu, Kun-Ru
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Zhang, Ling-Yan
Both cameras and IoT devices have their particular capabilities in tracking moving objects. Their correlations are, however, unclear. In this work, we consider using a drone to track ground objects. We demonstrate how to retrieve IoT data from devices, which are attached on human objects, and correctly tag them on the human objects captured by a drone view. This is the first work correlating IoT data and computer vision from a drone camera. Potential applications of this work include aerial surveillance, people tracking, and intelligent human-drone interaction.
Design of 2-D Digital Filters with Almost Quadrantal Symmetric Magnitude Response without 1-D Separable Denominator Factor Constraint
(2013)
Khoo, I-Hung
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Reddy, Hari C.
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Van, Lan-Da
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Lin, Chin-Teng
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資訊工程學系
A design approach is presented for 2-D digital filters possessing approximate quadrantal magnitude symmetry without the constraint of the denominator having only 1-D separable factors. To ensure the BIBO stability of the filter, the planar least square inverse stabilization approach is employed. It is illustrated through design examples that the proposed approach results in filters with sharper transition band and lower error relative to the given filter specifications. Also, for certain cases, it is shown that a lower order non-separable denominator design can achieve the same result as a higher order separable denominator design, thus providing savings in the number of multipliers. Finally, 2-D VLSI realizations without global broadcast are presented for the optimized transfer function with non-separable denominator factors and approximate quadrantal symmetry.