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Browsing by Author "WANG, HM"

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    ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITS
    (1994)
    WANG, HM
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    LEE, CL
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    CHEN, JE
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    電子工程學系及電子研究所
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    Department of Electronics Engineering and Institute of Electronics
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    COMPLETE TEST SET FOR MULTIPLE-VALUED LOGIC-NETWORKS
    (1994)
    WANG, HM
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    LEE, CL
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    CHEN, JE
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    電子工程學系及電子研究所
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    Department of Electronics Engineering and Institute of Electronics
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    FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITS
    (1993-06-01)
    WANG, HM
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    LEE, CL
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    CHEN, JE
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    交大名義發表
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    電子物理學系
    This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.