Browsing by Author "WANG, JS"

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ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC
(1993-01-01)
WU, CY
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CHENG, KH
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WANG, JS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structured as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design.
CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS
(1989-06-01)
WANG, JS
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WU, CY
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TSAI, MK
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電控工程研究所
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Institute of Electrical and Control Engineering
LOW-POWER DYNAMIC TERNARY LOGIC
(1988-12-01)
WANG, JS
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WU, CY
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TSAI, MK
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW
(1989-05-01)
WANG, JS
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WU, CY
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TSAI, MK
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電控工程研究所
;
Institute of Electrical and Control Engineering
THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC
(1987-02-01)
WU, CY
;
WANG, JS
;
TSAI, MK
;
電控工程研究所
;
Institute of Electrical and Control Engineering