Browsing by Author "WANG, KH"
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Item type:Item, Boolean matching for incompletely specified functions(1995) ;WANG, KH ;HWANG, TT ;資訊工程學系Department of Computer ScienceItem type:Item, LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS(1994-10-01) ;HWANG, TT ;OWENS, RM ;IRWIN, MJ ;WANG, KH資訊工程學系In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.Item type:Item, OVERLAPPED DECOMPOSITIONS FOR COMMUNICATION COMPLEXITY DRIVEN MULTILEVEL LOGIC SYNTHESIS(1993-09-01) ;WANG, KH ;HWANG, TT ;CHEN, C ;交大名義發表資訊工程學系Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting ''globals'' and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.Item type:Item, TECHNOLOGY MAPPING FOR FPGA USING GENERALIZED FUNCTIONAL DECOMPOSITION(1993) ;WANG, KH ;HWANG, TT ;CHEN, C ;資訊工程學系Department of Computer Science