Browsing by Author "WEI, CH"
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Item type:Item, A FAST ADAPTIVE RAM-BASED DECISION FEEDBACK EQUALIZER FOR PARTIAL-RESPONSE NONLINEAR RECORDING CHANNELS(1994) ;HWANG, HC ;WEI, CH ;電控工程研究所Institute of Electrical and Control EngineeringItem type:Item, A NEW VARIABLE FRACTIONAL SAMPLE DELAY FILTER WITH NONLINEAR INTERPOLATION(1992-02-01) ;LIU, GS ;WEI, CH ;交大名義發表 ;電控工程研究所National Chiao Tung UniversityThis paper presents a finite impulse response (FIR) filter that can synthesize any fractional sample delay by nonlinear interpolation technique. Analytically closed-form solutions for the tap weights of such an FIR filter and their frequency responses are presented.Item type:Item, ADAPTIVE NONLINEAR DECISION-FEEDBACK EQUALIZATION WITH CHANNEL ESTIMATION AND TIMING RECOVERY IN DIGITAL MAGNETIC RECORDING-SYSTEMS(1995-03-01) ;LIN, JY ;WEI, CH ;電控工程研究所 ;電信研究中心Institute of Electrical and Control EngineeringIn high density digital magnetic recording systems, the nonlinear effects in the write process appear in the readback waveform as shifts in the peak positions and changes in the amplitude, The pulse shift causes a nonlinear intersymbol interference (ISI) on the readback signal, In this paper, a Volterra-DFE, in which a Volterra filter is used in the feedback section of decision feedback structure, is proposed to equalize the nonlinear ISI, By theoretical analysis, the minimum mean squared error (MSE) of the Volterra-DFE is found to be a function of sampling phase. This will affect the output signal-to-noise ratio (SNR) of the playback system, A baud-rate timing recovery system in conjunction with channel estimator is used to operate the sampling clock on the optimum phase, By computer simulation, Volterra-DFE is found to outperform conventional DFE in both output SNR and BER in a high density magnetic recording system.Item type:Item, ADAPTIVE VOLTERRA-DFE AND TIMING RECOVERY IN DIGITAL MAGNETIC RECORDING SYSTEM(1994) ;LIN, JY ;WEI, CH ;電控工程研究所Institute of Electrical and Control EngineeringItem type:Item, AN ALTERNATIVE APPROACH FOR DESIGNING MAXIMALLY FLAT LOW-PASS FILTERS WITH MULTIPLE ORDER IMAGINARY-AXIS ZEROS(1986-06-01) ;WEI, CH ;交大名義發表 ;電子工程學系及電子研究所 ;National Chiao Tung UniversityDepartment of Electronics Engineering and Institute of ElectronicsItem type:Item, COMPLETE DECODING ALGORITHM OF (11, 6, 5) GOLAY CODE(1989-08-17) ;WEI, SW ;WEI, CH ;電控工程研究所 ;電信研究中心Institute of Electrical and Control EngineeringItem type:Item, CONVOLUTIONAL CODING FOR BPSK SYSTEM WITH ORTHOGONAL SOUNDING TONE ON FAST RAYLEIGH FADING CHANNEL(1986-11-20) ;CHEN, YL ;WEI, CH ;交大名義發表 ;電控工程研究所National Chiao Tung UniversityItem type:Item, DESIGN OF SHARP CUTOFF LOW-PASS MAXIMALLY FLAT RC-ACTIVE FILTERS BY CASCADING 3RD-ORDER BLOCKS(1980) ;WEI, CH ;交大名義發表 ;電控工程研究所 ;National Chiao Tung UniversityInstitute of Electrical and Control EngineeringItem type:Item, DIGITAL TANLOCK LOOP FOR TRACKING PI/4-DQPSK SIGNALS IN DIGITAL CELLULAR RADIO(1994-08-01) ;WEI, CH ;CHEN, WJ ;電控工程研究所 ;電信研究中心Institute of Electrical and Control EngineeringA digital tanlock loop (DTL) is a nonuniform-sampling digital phase-locked loop (DPLL) whose phase error detector, using the tan-1[.] function with in-phase and quadrature samples of incoming signal, has a linear characteristic with a period of 2pi. In this paper, we study the application of an N-phase DTL in digital cellular radio with pi/4-DQPSK modulation. The performance degradation due to fading effect is investigated in terms of bit error rate and steady state phase error variance by computer simulation. It is shown that, in the digital cellular radio system, the performances on both bit error rate and phase error variance using DTL are far better than that using the traditional digital N-phase I-Q loop.Item type:Item, EFFICIENT BIT-LEVEL SYSTOLIC ARRAY FOR THE LINEAR DISCRIMINANT FUNCTION CLASSIFIER(1987-10-01) ;WANG, CL ;WEI, CH ;CHEN, SH ;傳播研究所電控工程研究所Item type:Item, EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL-FILTERS(1988-04-01) ;WANG, CL ;WEI, CH ;CHEN, SH ;電控工程研究所電信工程研究所Item type:Item, FAST TIMING RECOVERY SCHEME FOR CLASS-IV PARTIAL-RESPONSE CHANNELS(1995-02-02) ;LIN, JY ;WEI, CH ;電控工程研究所 ;電信研究中心Institute of Electrical and Control EngineeringA timing recovery scheme with fast acquisition is proposed for a class IV partial response (PR-IV) magnetic recording system. The time information is obtained directly from the coefficients of the channel estimator. For initial adjustment of the time phase, a known preamble is sent ahead of the user data and a modified threshold decision is employed to avoid the hangup effect.Item type:Item, HIGH-SPEED DECODER OF REED-SOLOMON CODES(1993-11-01) ;WEI, SW ;WEI, CH ;電控工程研究所 ;電信研究中心Institute of Electrical and Control EngineeringA high speed decoding algorithm using a modified step-by-step method for t-error-correcting Reed-Solomon codes is introduced. Based on this algorithm, a sequential decoder and a vector decoder are then proposed. These two decoders can be constructed by four basic modules: the syndrome calculation module, the comparison module, the decision module, and the shift-control module. These decoders cao be applied for both binary and nonbinary data transmissions working at high data rate. Because of the simplicity in structure and circuit realization, a decoder employing this algorithm can be easily implemented in a monolithic chip by the VLSI technology.Item type:Item, HIGH-SPEED HARDWARE DECODER FOR DOUBLE-ERROR-CORRECTING BINARY BCH CODES(1989-06-01) ;WEI, SW ;WEI, CH ;交大名義發表 ;電子工程學系及電子研究所National Chiao Tung UniversityItem type:Item, HIGH-SPEED REED-SOLOMON DECODER FOR CORRECTING ERRORS AND ERASURES(1993-08-01) ;WEI, CH ;CHEN, CC ;LIU, GS ;電控工程研究所電信研究中心A Reed-Solomon decoder for errors-and-erasures correction, based on a new algebraic decoding algorithm, is presented. This high-speed decoder requires only n clock cycles for decoding each received n-symbol block. A serial structure that requires very few multipliers and provides a general expression to calculate the coefficients of the erasure-locator polynomial is also presented. A (15, 11) RS decoder and its shortened version (7, 3) RS decoder are used as design examples to illustrate the operating procedure of the new decoding algorithm.Item type:Item, IMPROVED SYSTOLIC ARRAY FOR LINEAR DISCRIMINANT FUNCTION CLASSIFIER(1986-01-16) ;WANG, CL ;WEI, CH ;CHEN, SH ;傳播研究所電控工程研究所Item type:Item, L(P) NORM BACK-PROPAGATION ALGORITHM FOR ADAPTIVE EQUALIZATION(1995-09-01) ;SIU, S ;CHANG, CH ;WEI, CH ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsThe l(p) norm back propagation algorithm for perceptron based adaptive equalization is analyzed taking account of possible numerical problem encountered when p < 1. Two methods are proposed to overcome the numerical problem. Computer simulations indicate that simultaneous improvement in convergence rate and bit-error-rate (BER) performance can be achieved by using p < 2.Item type:Item, L(P) NORM BACK-PROPAGATION ALGORITHM FOR ADAPTIVE EQUALIZATION(1995-09-01) ;SIU, S ;CHANG, CH ;WEI, CH ;電控工程研究所Institute of Electrical and Control EngineeringThe l(p) norm back propagation algorithm for perceptron based adaptive equalization is analyzed taking account of possible numerical problem encountered when p < 1. Two methods are proposed to overcome the numerical problem. Computer simulations indicate that simultaneous improvement in convergence rate and bit-error-rate (BER) performance can be achieved by using p < 2.Item type:Item, MANEUVERING TARGET TRACKING USING IMM METHOD AT HIGH MEASUREMENT FREQUENCY(1991-05-01) ;GUU, JA ;WEI, CH ;電控工程研究所Institute of Electrical and Control EngineeringIn tracking a maneuvering target by a radar system, the measurement noise is significantly correlated when the measurement frequency is high. In this paper, a simple decorrelation process is proposed to enhance the interacting multiple model (IMM) algorithm to track a maneuvering target with correlated measurement noise. It is found that the decorrelation process may improve system performance significantly, especially in velocity and acceleration estimations.Item type:Item, MULTIMEMORY BLOCK STRUCTURE FOR IMPLEMENTING A DIGITAL ADAPTIVE FILTER USING DISTRIBUTED ARITHMETIC(1986-02-01) ;WEI, CH ;LOU, JJ ;傳播研究所 ;電子工程學系及電子研究所Institute of Communication Studies