Browsing by Author "WEN, KS"

Now showing 1 - 2 of 2

A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
(1995-04-01)
WEN, KS
;
LI, HH
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An efficient and accurate 2D numerical simulation technique is developed to study the hot-electron effects on short-channel n-MOSFETs. The 1D substrate injection probability used by Ning el al, has been further modified by considering the channel hot-electron-enhanced injection probability. Moreover, the hot-electron-injection-induced Si/SiO2 interface-trap generation and its effects on MOSFET drain, substrate and gate currents have also been taken into consideration. It is shown that the generated electron traps at the Si/SiO2 interface enhance both the impact ionization rate and the degradation of MOSFET characteristics but retard the injection probability of hot electrons into the gate oxide. The spatial distribution of the generated Si/SiO2 interface traps calculated by our model has been well verified by the charge pumping measurement. In addition, the simulated substrate current, gate current, and degradation of drain current are in good agreement with the experimental results of a short-channel n-MOSFET with the oxide thickness of 100 Angstrom and the effective channel length of 0.45 mu m for wide ranges of drain and gate biases.
A SIMPLE AND ACCURATE SIMULATION TECHNIQUE FOR FLASH EEPROM WRITING AND ITS RELIABILITY ISSUE
(1995-07-01)
WEN, KS
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An efficient and accurate 2D analysis for gate-current is proposed for short channel n-MOSFETs, in which the channel hot-electron-enhanced injection probability is proposed and expressed in terms of the actual current path and its power density flow. The accuracy of our gate-current analysis has been verified by comparisons between simulation and experimental data. This well-established gate current analysis as well as the charge boundary condition on the floating gate have been implemented into the sub-micron MOS (SUMMOS) two-dimensional device simulator for characterizing n-channel flash EEPROM writing. Comparisons with experimental EEPROM writing have been made, and quite good agreements have been obtained for test devices with different channel lengths ranging from 0.8 to 0.5 mu m for wide range of applied biases. Moreover, computer simulation for EEPROM reliability issue caused by oxide electron traps has also been performed to characterize the endurance of flash EEPROM operation.