Browsing by Author "WU, TS"

Now showing 1 - 6 of 6

2-DIMENSIONAL ELECTRON GASES IN DELTA-DOPED GAAS/IN0.25GA0.75AS/GAAS HETEROSTRUCTURES
(1991-06-10)
LIN, W
;
HSU, WC
;
WU, TS
;
CHANG, SZ
;
WANG, C
Delta-doped (delta-doped) GaAs/In0.25Ga0.75As/GaAs strained-layer modulation-doped field-effect transistor (delta-SMODFET) structures grown by the low-pressure metalorganic chemical vapor deposition (LP-MOCVD) technique have been studied for the first time. The delta-doped GaAs, adopted as the electron supplier, was obtained by a stop-growth process so that a very thin and heavily doped layer (1.9 X 10(13) cm-2) can be realized. Experimental results show that a structure with an 80 angstrom In0.25Ga0.75As layer as the active channel and an 80 angstrom spacer layer demonstrated the highest two-dimensional electron gases mobility of 26 800 cm2/V s. This structure is easy to achieve by the LP-MOCVD method because the growth of AlGaAs is avoided and is promising for high performance FETs.
Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's
(1995)
KER, MD
;
WU, CY
;
CHANG, HH
;
CHENG, T
;
WU, TS
EFFECT OF FLUORINE INCORPORATION ON THE THERMAL-STABILITY OF PTSI/SI STRUCTURE
(1993-01-01)
TSUI, BY
;
TSAI, JY
;
WU, TS
;
CHEN, MC
;
交大名義發表
The effect of fluorine incorporation on PtSi/Si structure is studied systematically. It is observed that the fluorine incorporation from ion implantation improves the high-temperature stability of the PtSi/Si structure. The optimum implantation energy is determined to be the energy at which the maximum percentage of the as-implanted fluorine ion locates at the PtSi/Si interface region. The SIMS analysis shows that the fluorine atom piles up at the PtSi/Si interface. The XPS analysis indicates that the fluorine atoms at the PtSi/Si interface are bonded to the silicon atoms in a form of SiF2 or SiF3. A fluorine-buffer (FB) model is proposed to explain the effect of fluorine incorporation. It is postulated that the Si-F layer acts as a buffer layer to change the PtSi/Si interface energy and preserve the integrity of the silicide layer at high temperature. Fluorinated Schottky junctions are fabricated and the electrical characteristics show that the sustainable process temperature can be improved from 650-degrees-C for the unfluorinated Schottky junctions to higher than 800-degrees-C for the fluorinated Schottky junctions.
NEW PHYSICAL TIMING MODELS OF BIPOLAR NONSATURATION LOGIC USING CURRENT DOMAIN ANALYSIS TECHNIQUE
(1991-04-01)
WU, CY
;
WU, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new large-signal equivalent circuit with input and output current signals for a nonsaturated bipolar junction transistor has been developed. Based upon this equivalent circuit, physical timing models of direct-coupled transistor logic (DCTL) and nonthreshold logic (NTL) have been derived through a general modeling methodology. It is shown from extensive comparisons with SPICE simulation results that the models have a maximum error of 25% in single-stage delay calculation and 10% in multi-stage delay calculation. Experimental results on NTL ring oscillators also partly substantiate the developed current-domain large-signal equivalent circuit and physical timing models. Good accuracy, wide applicable ranges of device/circuit parameters and input waveforms, and less CPU time and memory consumption than full transient simulations make the physical timing models feasible in optimization and CAD of high-speed bipolar ICs.
PHYSICAL TIMING MODELS AND DESIGN METHODOLOGY OF BIPOLAR NONTHRESHOLD LOGIC-CIRCUITS
(1990-12-01)
WU, CY
;
WU, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Physical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C(E) and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C(E) is equal to 1-1.25 C(E0) where C(E0) is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C(E0) have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.
THE DELTA-DOPED IN0.25GA0.75AS/GAAS PSEUDOMORPHIC HIGH ELECTRON-MOBILITY TRANSISTOR STRUCTURES PREPARED BY LOW-PRESSURE METAL ORGANIC-CHEMICAL VAPOR-DEPOSITION
(1991-06-01)
CHANG, CY
;
LIN, W
;
HSU, WC
;
WU, TS
;
CHANG, SZ
The (800 angstrom)GaAs/In0.25Ga0.75As/(0.5-mu-m) GaAs strain layers with delta-doping in the GaAs cap layer were fabricated without using AlGaAs layers. Triethylgallium (TEG), trimethylindium (TMI), arsine (AsH3) and silane (SiH4) were used as the sources and dopants in these structures grown by the low-pressure metalorganic chemical vapor deposition (LP-MOCVD) technique for the first time to study these structures. The delta-doping was obtained by a stop-growth process by which a very thin and heavily doped layer (1.86 x 10(13) cm-2) can be realized. For the (delta-doped) GaAs/In0.25Ga0.75As/GaAs high electron mobility transistor (HEMT) structures, the concentration of two-dimensional electron gas (2-DEG) and the Hall mobilities were investigated. Experimental results show that a structure with (80 angstrom) In0.25Ga0.75As as the active channel and with a 70 angstroms spacer layer revealed the highest 2-DEG concentration and mobility product of 5.5 x 10(16) V-1.s-1 at a temperature of 77 K. These structures are easy to achieve by the LP-MOCVD mechod and are promising for high-performance field effect transistors (FETs).