Browsing by Author "Wang, Cheng-Yeh"

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A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
(2007-10-01)
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
(2006)
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each AID channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
Communication-driven task binding for multiprocessor with latency insensitive Network-on-Chip
(2005)
Lin, Liang-Yu
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Wang, Cheng-Yeh
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Huang, Pao-Jui
;
Chou, Chih-Chieh
;
Jou, Jing-Yang
Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.
Hierarchical Architecture for Network-on-Chip Platform
(2009)
Lin, Liang-Yu
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Lin, Huang-Kai
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Wang, Cheng-Yeh
;
Van, Lan-Da
;
Jou, Jing-Yang
In this paper, we propose one hierarchical 2-D mesh Network-on-Chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount, communication data contention and bandwidth penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation too] is also built. Therefore, architecture and designer.,; can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput, the latency, and the saving of redundant transactions are improved by 27%. 14.4% and 21.8% respectively under the communication dominated situation.
Hybrid word-length optimization methods of pipelined FFT processors
(2007-08-01)
Wang, Cheng-Yeh
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Kuo, Chih-Bin
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Jou, Jing-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Quickly and accurately predicting the performance based on the requirements for IP-based system implementations optimizes the design and reduces the design time and overall cost. This study describes a novel hybrid method for the word-length optimization of pipelined FFT processors that is the arithmetic kernel of OFDM-based systems. This methodology utilizes the rapid computing of statistical analysis and the accurate evaluation of simulation-based analysis to investigate a speedy optimization flow. A statistical error model for varying word-lengths of PE stages of an FFT processor was developed to support this optimization flow. Experimental results designate that the word-length optimization employing the speedy flow reduces the percentage of the total area of the FFT processor that increases with an increasing FFT length. Finally, the proposed hybrid method requires a shorter prediction time than the absolute simulation-based method does and achieves more accurate outcomes than a statistical calculation does.
Pre-charge sample-and-hold circuit
(2008-07-31)
Wu, Jieh-Tsorng
;
Lee, Zwei-Mei
;
Wang, Cheng-Yeh
A precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode, it precharges the total load capacitor. When the sample-and-hold circuit is in the hold mode, the influence to the sampled signal is further reduced due to the precharging. The requirements of swing rate, output voltage swing, gain-bandwidth product for the opamps can therefore be reduced, hence being applicable to the realization of the design of advanced fabrication technologies of low supply voltages.