Browsing by Author "Wang, Chin-Te"

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An 80 nm In(0.7)Ga(0.3)As MHEMT with Flip-Chip Packaging for W-Band Low Noise Applications
(2010-01-01)
Wang, Chin-Te
;
Kuo, Chien-I
;
Lim, Wee-Chin
;
Hsu, Li-Han
;
Hsu, Heng-Tung
The fabrication process of an 80 nm In(0.7)Ga(0.3)As MHEMT device with flip-chip packaging on Al(2)O(3) substrate is presented. The flip-chip packaged device exhibited good dc characteristics with high I(DS) = 425 mA/mm and high g(m) = 970 mS/mm at V(DS) = 1.5 V. Besides, the RF performances revealed high gain of 10 dB at 50 GHz and low minimum noise figure (NF(min))below 2 dB at 60 GHz, showing the feasibility of flip-chip packaged In(0.7)Ga(0.3)As MHEMT device for low noise applications at W-band.
An 80 nm In0.7Ga0.3As MHEMT with Flip-Chip Packaging for W-Band Low Noise Applications
(2010-01-01)
Wang, Chin-Te
;
Kuo, Chien-, I
;
Lim, Wee-Chin
;
Hsu, Li-Han
;
Hsu, Heng-Tung
The fabrication process of an 80 nm In0.7Ga0.3As MHEMT device with flip-chip packaging on Al2O3 substrate is presented. The flip-chip packaged device exhibited good dc characteristics with high I-DS = 425 mA/mm and high g(m) = 970 mS/mm at V-DS = 1.5 V. Besides, the RF performances revealed high gain of 10 dB at 50 GHz and low minimum noise figure (NFmin)below 2 dB at 60 GHz, showing the feasibility of flip-chip packaged In0.7Ga0.3As MHEMT device for low noise applications at W-band.
Assessment of Thermal Impact on Performance of Metamorphic High-Electron-Mobility Transistors on Polymer Substrates Using Flip-Chip-on-Board Technology
(2013-12-01)
Wang, Chin-Te
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Chang, Edward Yi
;
Lim, Wee-Chin
In this study, we have fabricated and characterized an In0.6Ga0.4As metamorphic high-electron-mobility transistor (mHEMT) device packaged using flip-chip-on-board (FCOB) technology. A low-cost polymer substrate was adopted as the carrier for cost-effective purposes. The impact of bonding temperature on the device performance was also experimentally investigated. While the DC performance was not as sensitive, serious degradation in RF performance was observed at high bonding temperature. Such degradation was mainly due to the thermal-mechanical stress resulting from the mismatch in the coefficient of thermal expansion (CTE) between the GaAs chip and the polymer substrate. Quantitative assessment was also performed through equivalent circuit extraction from S-parameter measurements. (C) 2013 The Japan Society of Applied Physics
Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications
(2010-02-01)
Hsu, Li-Han
;
Wu, Wei-Cheng
;
Chang, Edward Yi
;
Zirath, Herbert
;
Wu, Yun-Chi
This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.
Design of Flip-Chip Interconnect Using Epoxy-Based Underfill Up to V-Band Frequencies With Excellent Reliability
(2010-08-01)
Hsu, Li-Han
;
Wu, Wei-Cheng
;
Chang, Edward Yi
;
Zirath, Herbert
;
Hu, Yin-Chu
This study demonstrates a flip-chip interconnect with epoxy-based underfill (epsilon(r) = 3.5 and tan delta = 0.02 at 10 MHz) for packaging applications up to V-band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al(2)O(3) substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip interconnect showed excellent performance from dc to 67 GHz with return loss below -20 dB and insertion loss less than 0.6 dB. Furthermore, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 degrees C/85 % relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the S-parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
Design, Fabrication, and Reliability of Low-Cost Flip-Chip-On-Board Package for Commercial Applications up to 50 GHz
(2012-03-01)
Hsu, Li-Han
;
Oh, Chee-Way
;
Wu, Wei-Cheng
;
Chang, Edward Yi
;
Zirath, Herbert
This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technology skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (epsilon(r) = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss S-11 greater than 18 dB and insertion loss S-21 less than 0.5 dB. Meanwhile, the flip-chip bonding of the in-house-fabricated In0.52Al0.As-48/In0.6Ga0.4As metamorphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implementing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors' knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.
Flip-Chip Packaging of In0.6Ga0.4As MHEMT Device on Low-Cost Organic Substrate for W-Band Applications
(2010)
Lim, Wee Chin
;
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Li-Han
;
Tsai, Szu-Ping
A discrete low noise In0.6Ga0.4As MHEMT device with 150 nm gate length was flip-chip assembled on the low-cost RO3210 organic substrate for wireless communication applications. The measured DC characteristics were very similar before and after flip-chip assembly. The flip-chip packaged MHEMT device showed a high drain current density of 516 mA/mm and a maximum transconductance of 576 mS/mm at a V-DS of 0.8 V. The insertion gain of the flip-chip packaged device was decayed less than 2 dB up to 100 GHz as compared to the data of bare die. Moreover, the measured minimum noise figure was less than 2 dB as measured at V-DS of 0.7 V and V-GS of -0.7 V in the frequency range from 20 to 64 GHz for the device after flip-chip assembly. The excellent performance of the flip-chip packaged MHEMT device demonstrates the feasibility of using low cost organic substrate for high frequency applications up to W band.
Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-Cost Organic Substrate
(2011-09-01)
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Heng-Tung
;
Chang, Edward Yi
;
Hsu, Li-Han
The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this study, the in-house fabricated In(0).(6)Ga(0.4)As metamorphic high electron mobility transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained a low minimum noise figure of 3 dB with 6 dB associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band. (C) 2011 The Japan Society of Applied Physics
Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications
(2014-01-01)
Wang, Chin-Te
;
Hsu, Li-Han
;
Wu, Wei-Cheng
;
Hsu, Heng-Tung
;
Chang, Edward Yi
Flip-chip package has great potential for use in millimeter-wave applications. However, the coefficient of thermal expansion mismatch between the chip and the substrate usually generates thermal stresses that fracture the flip-chip structure. The use of underfills with low dielectric loss is essential to improve the mechanical strength and reliability of the flip-chip package. Benzocyclobutene (BCB) was used in this study as the underfill material for the flip-chip structure using the no-flow process. The flip-chip structure with BCB injection provides good RF performance with a return loss of better than 18 dB and an insertion loss of 0.6 dB up to 100 GHz, in addition to a lower dielectric loss. Furthermore, thermal cycle and shear force tests show that the underfill injection can significantly improve the reliability of a flip-chip package.
V-Band Flip-Chip Assembled Gain Block Using In(0.6)Ga(0.4)As Metamorphic High-Electron-Mobility Transistor Technology
(2011-10-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Heng-Shou
This study fabricated a 150 nm In(0.6)Ga(0.4)As metamorphic high-electron-mobility transistor (mHEMT) device with flip-chip packaging. The packaged device exhibited favorable DC characteristics with I(DS) = 350 mA/mm and a transconductance of 600 mS/mm at V(DS) = 0.5V. A maximum available gain (MAG) of 6.5 dB at 60 GHz was achieved with 10 mW DC power consumption. A two-stage gain block was designed and fabricated. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20 mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal-oxide-semiconductor (CMOS) technology with lower power consumption. (C) 2011 The Japan Society of Applied Physics
V-Band Flip-Chip Assembled Gain Block Using In0.6Ga0.4As Metamorphic High-Electron-Mobility Transistor Technology
(2011-10-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Heng-Shou
This study fabricated a 150 nm In0.6Ga0.4As metamorphic high-electron-mobility transistor (mHEMT) device with flip-chip packaging. The packaged device exhibited favorable DC characteristics with I-DS = 350 mA/mm and a transconductance of 600 mS/mm at V-DS = 0.5V. A maximum available gain (MAG) of 6.5 dB at 60 GHz was achieved with 10 mW DC power consumption. A two-stage gain block was designed and fabricated. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20 mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal-oxide-semiconductor (CMOS) technology with lower power consumption. (C) 2011 The Japan Society of Applied Physics