Browsing by Author "Wang, Ching-Chiun"

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A process for high yield and high performance carbon nanotube field effect transistors
(2010-05-01)
Lee, Tseng-Chin
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Tsui, Bing-Yue
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Tzeng, Pei-Jer
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Wang, Ching-Chiun
;
Tsai, Ming-Jinn
Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 mu S, and high I(on)/I(off) ratio of 10(6) can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. (C) 2010 Elsevier Ltd. All rights reserved.
Characterization of Al2O3/ZnO Grown on Si Substrate by Plasma Enhanced Atomic Layer Deposition
(2013-01-01)
Chung, Chen-Chen
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Tran, Binh-Tinh
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Lin, Kung-Liang
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Wang, Ching-Chiun
;
Chen, Chien-Chih
Characterization of nanolaminate Al2O3/ZnO oxide films grown on Si substrates was conducted by using plasma enhanced atomic layer deposition (PE-ALD) method. PE-ALD can minimize the structural imperfections in films and reduce substrate damage. The film deposition by using PE-ALD are dense, defect-free, highly uniform, conformal films and show excellent step coverage. Moreover, compared to other deposition techniques, it is possible to deposit high quality films at much lower temperatures. High resolution transmission electron microscope (TEM) images showed the existence of sharp interfacial layers among the Al2O3, ZnO layer, and the Si substrate for the growth rate of 1.56 angstrom/cycle, and the surface roughness of about 0.2 nm. The nanolaminate-stacking layer can be used in organic light emitting diode encapsulation application as the gas barrier.
Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate
(2009-04-01)
Lu, Chi-Pei
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Luo, Cheng-Kei
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Tsui, Bing-Yue
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Lin, Cha-Hsin
;
Tzeng, Pei-Jer
In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al(2)O(3) high-k blocking dielectric layer and a P(+) polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al(2)O(3) nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 10(3) s stressing bias. (C) 2009 The Japan Society of Applied Physics
Trigate TiN Nanocrystal Memory with High-k Blocking Dielectric and High Work Function Gate Electrode
(2009)
Lu, Chi-Pei
;
Tsui, Bing-Yue
;
Luo, Cheng-Kei
;
Lin, Cha-Hsin
;
Tzeng, Pei-Jer
In this work, high-performance TiN metal nanocrystal nonvolatile memories using a p(+) poly-Si gate and a Al(2)O(3) blocking dielectric layer with trigate structure are fabricated on silicon-on-insulator substrate. Devices with moderate transistor performance and superior memory properties are demonstrated. A memory window as high as 5 V is achieved after Program/Ease (P/E) operation at +/- 10 V for 0.1 s, with only 18 and 33% charge loss at room temperature and at 85 degrees C after 10 years storage. Only +0.5 V window shift and almost no window narrowing after 10(5) P/E operations can be obtained. Furthermore, a device with larger nanocrystals has better P/E characteristics and superior retention performance. (C) 2008 The Electrochemical Society. [DOI: 10.1149/1.3054304] All rights reserved.