Browsing by Author "Wang, Chun-Kai"

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A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit
(2011)
Wang, Chun-Kai
;
Chen, Che-Sheng
;
Wen, Kuei-Ann
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/root Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.
A Monolithic CMOS MEMS Accelerometer with Low Noise Gain Tunable Interface in 0.18 mu m CMOS MEMS Technology
(2012)
Lin, Yi-Da
;
Lin, Jian-Yuan
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Wang, Chun-Kai
;
Fan, Long-Sheng
;
Wen, Kuei-Ann
A monolithic capacitance accelerometer is fabricated in 0.18 mu m ASIC-compatible CMOS MEMS technology and, with the assistant of universal sensing system being developed in the proposed work. The new approach combines the Dual-Chopper amplifier and Correlated Double Sampling to alleviate 1/f noise and DC offset. The total noise equivalent acceleration is 13.49ug/root Hz under 500 Hz. The tunable sensitivity can be adjusted from 324.8 mV/fF to 17807.11mV/fF (differential mode) by the fully-differential variable gain amplifier (VGA).
An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
(2017-01-01)
Wu, Wan-Ning
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Chen, Chen
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Chin, Ching-Yu
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Wang, Chun-Kai
;
Chen, Hung-Ming
Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. With the physical information from the initial placement, we implement an affinity-based clustering algorithm while taking the control signal constraints into consideration. In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation and cell inflation. An incremental placer is performed after the global placement for closing the gap between the global placement and legalization, and a detailed placer is adopted to legalize the blocks and reduce the proposed methodologies can effectively improve the placement solutions.
Analysis for Efficiency Improvement of CMOS Class-E Power Amplifiers with MEMS Inductors
(2009)
Tsou, Wen-An
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Chen, Che-Sheng
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Wang, Chun-Kai
;
Chen, Kevin C. J.
;
Wu, Svu-Hsien
This paper presents an analysis and enhancement of efficiency in a class-E power amplifier using MEMS inductors. The M EMS technology is proposed and demonstrated by a prototype inductor. The model of MEMS inductors is created by HFSS simulator and its simulated result has good match with the measured result. Stacked-metal layer inductors in MEMS process are also developed to increase the quality factor. The simulation result of a CMOS class-E PA with MEMS inductors shows that the increased quality factor of inductors by 2 can improve the PA's efficiency by 6%. Furthermore, we present a design methodology for optimizing the PA's efficiency.
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
(2014-11-01)
Wang, Chun-Kai
;
Chang, Yeh-Chi
;
Chen, Hung-Ming
;
Chin, Ching-Yu
;
電子工程學系及電子研究所
This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.
Influences of Structural Modification of S,N-Hexacenes on the Morphology and OFET Characteristics
(2019-06-19)
Huang, Yi-Fan
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Wang, Chun-Kai
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Lai, Bo-Han
;
Chung, Chin-Lung
;
Chen, Chin-Yi
Although chemical modifications on conjugated molecules are widely applied for the purpose of improving processability and device performances, the effect of the modification was far less investigated. Here, five S,N-hexacenes are studied to reveal the influences of (1) the lateral alkyl chain, (2) the terminal group (thiophene vs benzene), and (3) the end capping phenyl group of the hexacenes on the morphology and organic field-effect transistor (OFET) performances. Crystal arrays of the hexacenes were prepared via polydimethylsiloxane (PDMS)-assisted crystallization (PAC) prior to morphological and OFET characterizations. The lattice structures and crystal quality of the hexacenes were evaluated by microscopy and diffraction techniques including single-crystal diffractometer, electron diffraction, and grazing incidence wide-angle X-ray scattering. The systematic analyses led to the following conclusions: (1) the bulkier alkyl side chain assists to form more densely packed crystals with less structural defects; (2) the terminal thiophene rings bring about higher-lying E-HOMO, more ordered phase, and crystal orientation, whereas the terminal benzene rings deteriorate the structural order of the active layer and result in the liquid crystal phase; and (3) the phenyl end caps ameliorate the morphological order, intermolecular overlapping, thermal stability and elevate E-HOMO. Thus, EH-DTPTt-Ph delivers the highest mu(h), contributing to high-lying E-HOMO, well-oriented crystal array with a longer correlation length, and suitable lattice orientation. This systematic research provides the aspects about the effects of the functionalized S,N-hexacenes on the morphology and OFET characteristics, which is anticipated to be useful for the molecular design of heteroacenes.
On Constructing Low Power and Robust Clock Tree via Slew Budgeting
(2012)
Chang, Yeh-Chi
;
Wang, Chun-Kai
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Clock skew resulted by process variation becomes more and more serious as technology shrinks. In 2010, ISPD held a high performance clock network synthesis contest; it considered supply-voltage variation and wire manufacturing variation. Previous works show that the main issue of variation induced skew is on supply-voltage variation. To trade off power and supply-voltage variation induced skew more effectively, we adapt a tree topology which use a timing model independent symmetrical tree at top level to drive the bottom level non-symmetry trees. Our method gives top tree more power budget to reduce supply-voltage variation induced skew and greedily saves power consuming in bottom level. Experimental results are evaluated from the benchmarks of ISPD contest 2010. Compared with state-of-the-art cross link work, the proposed technique reduces 10% of power consumption on average and also improves the run time.