Browsing by Author "Wang, Chun-Yao"

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Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
(2018-01-01)
Wu, Chia-Cheng
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Ho, Kung-Han
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Huang, Juinn-Dar
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Wang, Chun-Yao
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電子工程學系及電子研究所
Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.
Verification of pin-accurate port connections
(2008-09-01)
Lee, Geeng-Wei
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Huang, Juinn-Dar
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Wang, Chun-Yao
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Jou, Jing-Yang
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電子工程學系及電子研究所
Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.