Browsing by Author "Wang, D. P."

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A 45nm dual-port SRAM with write and read capability enhancement at low voltage
(2007)
Wang, D. P.
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Lia, H. J.
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Yamauchi, H.
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Chen, Y. H.
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Lin, Y. L.
This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.
InN nanotips as excellent field emitters
(2008-03-24)
Wang, K. R.
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Lin, S. J.
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Tu, L. W.
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Chen, M.
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Chen, Q. Y.
Unidirectional single crystalline InN nanoemitters were fabricated on the silicon (111) substrate via ion etching. These InN nanoemitters showed excellent field emission properties with the threshold field as low as 0.9 V/mu m based on the criterion of 1 mu A/cm(2) field emission current density. This superior property is ascribed to the double enhancement of (1) the geometrical factor of the InN nanostructures and (2) the inherently high carrier concentration of the degenerate InN semiconductor with surface electron accumulation layer induced downward band bending effect that significantly reduced the effective electron tunneling barrier even under very low external field. (c) 2008 American Institute of Physics.