Browsing by Author "Wang, Huan-Chung"

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A simple extraction method for parasitic series resistances in GaN HEMTs considering non-quasi-static effects
(2019-05-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Wang, Huan-Chung
;
Singh, Sankalp Kumar
;
Anandan, Deepak
A simple technique for extracting the bias-dependent parasitic series resistances of the GaN-based high electron mobility transistor (HEMT) is demonstrated in this paper. With considering the non-quasi-static effect in devices, new analytical Z-parameter formulations are derived to determine parasitic resistances using the curve-fitting algorithm. More accuracy parasitic resistances can be obtained over a wide fitting frequency range compared to the conventional method which ignores the non-quasi-static effect. Here the intrinsic parameters are then calculated directly from intrinsic Y-parameters after de-embedding the parasitic elements in the small-signal equivalent circuit. An excellent agreement between the measured and simulated S-parameters from 100 MHz to 40 GHz is achieved, which validates the feasibility of our method for extracting the bias-dependent parasitic resistances.
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
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Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
Effect of Postdeposition Annealing Temperatures on Electrical Characteristics of Molecular-Beam-Deposited HfO2 on n-InAs/InGaAs Metal-Oxide-Semiconductor Capacitors
(2012-02-01)
Trinh, Hai-Dang
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Lin, Yueh-Chin
;
Wang, Huan-Chung
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Chang, Chia-Hua
;
Kakushima, Kuniyuki
The electrical characteristics of molecular-beam-deposited HfO2/n-InAs/InGaAs metal-oxide-semiconductor capacitors with different postdeposition annealing (PDA) temperatures (400-550 degrees C) are investigated. Results show that the sample with the PDA temperature of 500 degrees C exhibits the best capacitance-voltage (C-V) behavior with small frequency dispersion and small hysteresis. The X-ray photoelectron spectroscopy (XPS) spectra show the reduction of the amount of As-related oxides to below the XPS detection level when the PDA temperature is up to 500 degrees C. As the PDA temperature was increased to above 500 degrees C, As and In atoms seem to diffuse significantly into HfO2, resulting in the degradation of C-V behavior. (C) 2012 The Japan Society of Applied Physics
GaN MIS-HEMTs With Nitrogen Passivation for Power Device Applications
(2014-10-01)
Liu, Shih-Chien
;
Chen, Bo-Yuan
;
Lin, Yueh-Chin
;
Hsieh, Ting-En
;
Wang, Huan-Chung
A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
High-Performance LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs With 850-V 0.98-m Omega.cm(2) for Power Device Applications
(2018-01-01)
Wang, Huan-Chung
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Lumbantoruan, Franky Juanda
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Hsieh, Ting-En
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Wu, Chia-Hsun
;
Lin, Yueh-Chin
We demonstrate the electrical performances of the quaternary InAlGaN/GaN MIS-HEMTs with high quality SiNx gate dielectric and surface passivation layer deposited by low pressure chemical vapor deposition (LPCVD) at 780 degrees C. Excellent LPCVD-SiNx/InAlGaN interface and SiNx film quality were obtained, resulting in very high output current density, a very small threshold voltage hysteresis and steep subthreshold slope. The LPCVD-SiNx/InAlGaN/GaN MIS-HEMT device exhibited high on/off current ratio, large gate voltage swing, high breakdown voltage, and very low dynamic on-resistance (R-ON) degradation, meaning effective current collapse suppression compared to the plasma enhanced chemical vapor deposition -SiN x /InAlGaN/GaN MIS-HEMTs. The corresponding specific on-resistance (RoN, sp ) for LPCVD-SiN x device was as low as 0.98 m Omega.cm(2), yielding a high figure of merit of 737 MW/cm(2) . These results demonstrate a great potential of the LPCVD-SiNx /InAlGaN/GaN MIS-HEMTs for high-power switching applications.
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
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Liu, Shih-Chien
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Hsieh, Ting-En
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Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
Improved Linearity in AlGaN/GaN HEMTs for Millimeter-Wave Applications by Using Dual-Gate Fabrication
(2017-01-01)
Wang, Huan-Chung
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Su, Huan-Fu
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Luc, Quang-Ho
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Lee, Ching-Ting
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Hsu, Heng-Tung
An effective method of improving the linearity of AlGaN/GaN HEMTs by using dual-gate technology is demonstrated. In this letter, we compare the DC characteristics and device linearity of the dual-gate AlGaN/GaN HEMTs with conventional single-gate AlGaN/GaN HEMTs. The correlation between the extrinsic transconductance (Gm) with third-order intermodulation distortion (IM3) and third order intercept point (IP3) suggests that the broader Gm distribution as a function of gate-bias, causes a lower IM3 level and higher IP3 values for the device. The improved device linearity demonstrates that dual-gate AlGaN/GaN HEMT design is a good approach for high-linearity RF device applications. (c) The Author(s) 2017. Published by ECS. All rights reserved.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
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Han, Ping-Cheng
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Quang Ho Luc
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Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
Normally-Off Tri-Gate GaN MIS-HEMTs with 0.76 m Omega center dot cm(2) Specific On-Resistance for Power Device Applications
(2019-08-01)
Wu, Chia-Hsun
;
Chen, Jian-You
;
Han, Ping-Cheng
;
Lee, Ming-Wen
;
Yang, Kun-Sheng
A GaN metal-insulator-semiconductor high electronmobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge-trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V-th) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R-ON) and high positive V-th. The designed tri-gate device exhibits a high V-th of +2.61 V at current density (I-DS) = 1 mu A/mm, a high maximum current density (I-DS, MAX) of 896 mA/mm, a low R-ON of 5.0 Omega center dot mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R-ON,R- SP) among reported normallyoff GaN device results with BV > 650 V.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
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Hsu, Heng-Tung
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Chiang, Che-Yang
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Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.