Browsing by Author "Wang, Huan-Hsiung"

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A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs
(2014-07-01)
Chen, Ming-Jer
;
Tu, Kong-Chiang
;
Wang, Huan-Hsiung
;
Chen, Chuan-Li
;
Lai, Shiou-Yi
Trapping-detrapping of a single electron via an individual trap in metal-oxide-semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude Delta I-d/I-d in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: (Delta I-d/I-d) = (I-loc/I-d)(2), where I-loc is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a 35 x 35-nm(2) channel to provide Delta I-d/I-d for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the I-loc/I-d formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.
Graphically Transforming Mueller-Schulz Percolation Criteria to Random Telegraph Signal Magnitudes in Scaled FETs
(2015-03-01)
Chen, Ming-Jer
;
Tu, Kong-Chiang
;
Chuang, Li-Yang
;
Wang, Huan-Hsiung
;
電子工程學系及電子研究所
We propose a novel graphic method to enable the analysis of the field-effect transistor (FET) threshold voltage variation Delta V-th due to random telegraph signals in a percolative channel. First, through technology computer-aided design simulation with no percolation, both a minimum Delta V-th and a critical curve in a m(loc) - sigma(loc) plot are produced. The former constitutes a statistical distribution far away from the conventional log-normal one. In the latter, m(loc) and sigma(loc) are the mean and the standard deviation, respectively, of a well-known normal variable in Mueller-Schulz\'s percolation theory. The critical m(loc) - sigma(loc) curve divides the plot into the allowed region and the forbidden region and will go down with increasing gate size. Then, Delta V-th contours in the allowed region are graphically created. While applying to existing experimental Delta V-th statistical distributions of SiON- and high-k metal gate (HKMG)-scaled FETs, resulting paired m(loc) and sigma(loc) at high Delta V-th remain intact, regardless of gate size or gate stack type. This means that the underlying percolation patterns resemble each other, due to the same manufacturing process used. However, if these paired m(loc) and sigma(loc) fall in the forbidden region, it is the critical m(loc) - sigma(loc) curve dominating. Application to bias and temperature instability statistical data in literature is straightforwardly well done.