Browsing by Author "Wang, I-Ting"

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3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation
(2014)
Wang, I-Ting
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Lin, Yen-Chuan
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Wang, Yu -Fen
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Hsu, Chung-Wei
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Hou, Tuo-Hung
A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<10 fJ/spike) has been demonstrated for the first time.
3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
(2016-09-09)
Wang, I-Ting
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Chang, Chih-Cheng
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Chiu, Li-Wen
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Chou, Teyuh
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Hou, Tuo-Hung
The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.
3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
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Wan, Chia-Chen
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Wang, I-Ting
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Chen, Mei-Chin
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Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
Bipolar Ni/TiO2/HfO2/Ni RRAM With Multilevel States and Self-Rectifying Characteristics
(2013-07-01)
Hsu, Chung-Wei
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Hou, Tuo-Hung
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Chen, Mei-Chin
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Wang, I-Ting
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Lo, Chun-Li
To be compatible with 3-D vertical crossbar arrays, a TiO2/HfO2 bilayer resistive-switching memory (RRAM) cell sandwiched between Ni electrodes is developed. The proposed device has numerous highly desired features for the implementation of 3-D vertical RRAM, including: 1) stable bipolar resistive switching; 2) forming free; 3) self-compliance; 4) self-rectification; 5) multiple resistance states; and 6) room-temperature process. The resistive switching and current rectification are attributed to oxygen vacancy migration in HfO2 and potential barrier modulation of the asymmetric TiO2/HfO2 tunnel barrier. The rectification ratio up to 10(3) is capable of realizing a single-crossbar array up to 16 Mb for future high-density storage class memory applications.
Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
(2015-08-01)
Liu, Jen-Chieh
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Hsu, Chung-Wei
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Wang, I-Ting
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Hou, Tuo-Hung
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電子工程學系及電子研究所
This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
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Liu, Jen-Chieh
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Shen, Yu-Lin
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Chou, Teyuh
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Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device
(2015-05-08)
Wang, Yu-Fen
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Lin, Yen-Chuan
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Wang, I-Ting
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Lin, Tzu-Ping
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Hou, Tuo-Hung
A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.
Development of Three-Dimensional Synaptic Device and Neuromorphic Computing Hardware
(2016-01-01)
Wang, I-Ting
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Chou, Teyuh
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Chiu, Li-Wen
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Chang, Chih-Cheng
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Hou, Tuo-Hung
To facilitate the development of low-cost, low-power, and high-density hardware neural networks, we have successfully developed a Ta/TaOx/TiO2/Ti RRAM-based synaptic device. The device exhibits numerous synaptic functions resembling those in biological synapses, including synaptic plasticity of potentiation and depression, spike-timing dependent plasticity, paired-pulse facilitation and a transition from short-term to long-term memory. We further demonstrate 3D high-density, high-connectivity integration of the Ta/TaOx/TiO2/Ti device, and the device exhibits excellent uniformity among interlayer and intralayer cells in a 4 x 4 3D two-layer cross-point array. Finally, we investigate the influence of nonlinearity of synaptic weight updates on neuromorphic computing. A state-independent training scheme is proposed to improve linearity and fault tolerance of training accuracy.
Dynamical modeling and experimental validation of a micro-speaker with corrugated diaphragm for mobile phones
(2007-05-01)
Chao, Paul C. -P.
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Wang, I-Ting
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電控工程研究所
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Institute of Electrical and Control Engineering
As the design trend of modern cellular phones evolves to be miniaturization and versatile sound in quality, the electro-mechanical components including the micro-speaker are essential toward size reduction and broad frequency range of sound. To reduce size, a diaphragm type micro-speaker is commonly employed in industry, while to broaden the sound frequency range corrugations on the diaphragm are adopted. The corrugations are generally capable of leading to fairly flat response over a broad range since diaphragm stiffness is decreased in axial direction. To confirm the aforementioned capability, the modeling on a corrugated diaphragm is performed first using finite element method (FEM) to obtain the associated dynamic equations in terms of modal coordinates; then the equations are next combined with the magneto-electrical model of the voice coil motor (VCM) that is attached to the bottom side of the diaphragm. Finally, the acoustic effects of the air inertia on the diaphragm and vents of the outer case are modeled using basic acoustic theories. Assembling all derived system equations and solving them, the frequency response of the micro-speaker in sound pressure level (SPL) can be simulated. It shows that the diaphragm corrugation in fact helps flatten the SPL response of the microspeaker (especially in high frequency range) to lessen sound distortion. Furthermore, the corrugation angle approximately below 45 degrees is favored over other angles or flatter SPL response. Experiments are also conducted to verify the theoretical findings.
Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTs
(2013-10-01)
Wu, Shih-Chieh
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Feng, Hsien-Tsung
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Yu, Ming-Jiue
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Wang, I-Ting
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Hou, Tuo-Hung
This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8 x 10(6), a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm(2)/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications.
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
(2015-11-13)
Gao, Ligang
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Wang, I-Ting
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Chen, Pai-Yu
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Vrudhula, Sarma
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Seo, Jae-Sun
A neuro-inspired computing paradigm beyond the von Neumann architecture is emerging and it generally takes advantage of massive parallelism and is aimed at complex tasks that involve intelligence and learning. The cross-point array architecture with synaptic devices has been proposed for on-chip implementation of the weighted sum and weight update in the learning algorithms. In this work, forming-free, silicon-process-compatible Ta/TaOx/TiO2/Ti synaptic devices are fabricated, in which >200 levels of conductance states could be continuously tuned by identical programming pulses. In order to demonstrate the advantages of parallelism of the cross-point array architecture, a novel fully parallel write scheme is designed and experimentally demonstrated in a small-scale crossbar array to accelerate the weight update in the training process, at a speed that is independent of the array size. Compared to the conventional row-by-row write scheme, it achieves >30x speed-up and >30x improvement in energy efficiency as projected in a large-scale array. If realistic synaptic device characteristics such as device variations are taken into an array-level simulation, the proposed array architecture is able to achieve similar to 95% recognition accuracy of MNIST handwritten digits, which is close to the accuracy achieved by software using the ideal sparse coding algorithm.
Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
(2014-04-25)
Hsu, Chung-Wei
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Wang, Yu-Fen
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Wan, Chia-Chen
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Wang, I-Ting
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Chou, Chun-Tse
Three-dimensional vertical resistive-switching random access memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10(3) with a sub-mu A operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10(15) cycles at 100 degrees C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.
Interface engineered HfO2-based 3D vertical ReRAM
(2016-06-02)
Hudec, Boris
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
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Jancovic, Peter
We demonstrate a double-layer 3D vertical resistive random access memory (ReRAM) stack implementing a Pt/HfO2/TiN memory cell. The HfO2 switching layer is grown by atomic layer deposition on the sidewall of a SiO2/TiN/SiO2/TiN/SiO2 multilayer pillar. A steep vertical profile was achieved using CMOS-compatible TiN dry etching. We employ in situ TiN bottom interface engineering by ozone, which results in (a) significant forming voltage reduction which allows for forming-free operation in AC pulsed mode, and (b) non-linearity tuning of low resistance state by current compliance during Set operation. The vertical ReRAM shows excellent read and write disturb immunity between vertically stacked cells, retention over 10(4) s and excellent switching stability at 400 K. Endurance of 10(7) write cycles was achieved using 100 ns wide AC pulses while fast switching speed using pulses of only 10 ns width is also demonstrated. The active switching region was evaluated to be located closer to the bottom interface which allows for the observed high endurance.
Investigating MLC Variation of Filamentary and Non-filamentary RRAM
(2014-01-01)
Liu, Jen-Chieh
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Wang, I-Ting
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Hsu, Chung-Wei
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Luo, Wun-Cheng
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Hou, Tuo-Hung
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
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Chen, Pin-Chun
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Chou, Teyuh
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Wang, I-Ting
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Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning
(2015-01-01)
Chen, Pai-Yu
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Lin, Binbin
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Wang, I-Ting
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Hou, Tuo-Hung
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Ye, Jieping
The cross-point array architecture with resistive synaptic devices has been proposed for on-chip implementation of weighted sum and weight update in the training process of learning algorithms. However, the non-ideal properties of the synaptic devices available today, such as the nonlinearity in weight update, limited ON/OFF range and device variations, can potentially hamper the learning accuracy. This paper focuses on the impact of these realistic properties on the learning accuracy and proposes the mitigation strategies. Unsupervised sparse coding is selected as a case study algorithm. With the calibration of the realistic synaptic behavior from the measured experimental data, our study shows that the recognition accuracy of MNIST handwriting digits degrades from similar to 97 % to similar to 65 %. To mitigate this accuracy loss, the proposed strategies include 1) the smart programming schemes for achieving linear weight update; 2) a dummy column to eliminate the off-state current; 3) the use of multiple cells for each weight element to alleviate the impact of device variations. With the improved synaptic behavior by these strategies, the accuracy increases back to similar to 95 %, enabling the reliable integration of realistic synaptic devices in the neuromorphic systems.
Multi-Bit-per-Cell a-IGZO TFT Resistive-Switching Memory for System-on-Plastic Applications
(2012)
Wu, Shih-Chieh
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Feng, Hsien-Tsung
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Yu, Ming-Jiue
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Wang, I-Ting
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Hou, Tuo-Hung
We reported a novel flexible nonvolatile memory using complete logic-compatible a-IGZO TFTs fabricated at room temperature. The memory device utilized localized and independent resistive switching for high-density two-bit-per-cell and multi-bit-per-cell operations. Combining low-temperature fabrication, low-cost integration, high bit-density, and excellent flexible memory characteristics, this device shows promise for future system-on-plastic applications.
Three dimensional integration of ReRAMs
(2018-01-01)
Hudec, Boris
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Chang, Che-Chia
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Wang, I-Ting
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Frohlich, Karol
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Hou, Tuo-Hung
Storage-class memory, non-volatile, ultra-dense and lightning fast, may enable memory-driven computing to revolutionize the current architectures leading to an on-chip processing of vast amount of data. 3D vertical resistive random access memory (ReRAM) is a hot candidate for storage-class memory. In this talk we review current state-of-the-art works which offer promising solutions, utilizing either filamentary or non-filamentary ReRAM designs, including our own. We will discuss the pros and cons of different approaches and summarize the open problems, drawing possible solutions.